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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 128/172頁(yè) |
| 文件大小： | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
128
Datasheet
APIC Configuration Space (FEC0_0000h –FECF_FFFFh,
FEE0_0000h– FEEF_FFFFh)
This range is reserved for APIC configuration space, which includes the default I/O APIC configuration
space. The default Local APIC configuration space is FEE0_0000h to FEEF_0FFFh.
Processor accesses to the local APIC configuration space do not result in external bus activity since the
local APIC configuration space is internal to the processor. However, a MTRR must be programmed to
make the local APIC range uncacheable (UC). The local APIC base address in each processor should be
relocated to the FEC0_0000h (4 GB – 20 MB) to FECF_FFFFh range so that one MTRR can be
programmed to 64 KB for the local and I/O APICs.
The I/O APIC(s) usually reside in the I/O Bridge
portion (I/O Controller Hub) of the chipset or as a stand-alone component(s).
I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/O APIC will be
located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h where
x
is I/O APIC unit number
0 through F(hex). This address range will be normally mapped via the hub interface to PCI.
Note:
There is no provision to support an I/O APIC device on AGP
The address range between the APIC configuration space and the High BIOS (FED0_0000h to
FFDF_FFFFh) is always mapped via the hub interface to PCI.
High BIOS Area (FFE0_0000h –FFFF_FFFFh)
The top 2 MB of the extended memory region is reserved for system BIOS (High BIOS), extended BIOS
for PCI devices, and the A20 alias of the system BIOS. The processor begins execution from the High
BIOS after reset. This region is mapped via the hub interface to PCI so that the upper subset of this
region aliases to 16 MB–256 MB range
.
The actual address space required for the BIOS is less than
2 MB but the minimum processor MTRR range for this region is 2 MB so that full 2 MB must be
considered. The I/O Controller Hub supports a maximum of 1 MB in the High BIOS range.
4.1.3.1.
System Management Mode (SMM) Memory Range
The GMCH supports the use of main memory as System Management RAM (SMRAM) enabling the use
of System Management Mode (SMM). The GMCH supports three SMM options: Compatible SMRAM
(AB segment enabled), High Segment (HSEG), and Top of Memory Segment (TSEG). System
Management RAM (SMRAM) space provides a memory area that is available for the SMI handler’s
code and data storage. This memory resource is normally hidden from the operating system so that the
processor has immediate access to this memory space upon entry to SMM. The GMCH provides three
SMRAM options:
Below 1 MB option that supports compatible SMI handlers.
Above 1 MB option that allows new SMI handlers to execute with write-back cacheable SMRAM.
Optional larger write-back cacheable T_SEG area of either 512 KB or 1MB in size above 1 MB
that is reserved from the highest area in system DRAM memory. The above 1 MB solutions
require changes to compatible SMRAM handler’s code to properly execute above 1 MB.
Refer to the
Power Management
section for more details on SMRAM support.
Note:
The hub interface and AGP masters are not allowed to access the SMM space. This must be insured even
for the GTLB translation.
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