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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 135/172頁(yè) |
| 文件大?。?/td> | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
Datasheet
135
4.4.2.
Special Cycles
A Special Cycle is defined when REQa[4:0] = 01000 and REQb[4:0]= xx001. The first address phase
Aa[35:3]# is undefined and can be driven to any value. The second address phase, Ab[15:8]# defines the
type of Special Cycle issued by the processor.
Table 12 specifies the cycle type and definition as well as the action taken by the GMCH when the
corresponding cycles are identified.
Table 12. Special Cycles
BE[7:0]#
Special Cycle Type
Action Taken
0000 0000
NOP
This transaction has no side-effects.
0000 0001
Shutdown
This transaction is issued when an agent detects a severe software error
that prevents further processing. This cycle is claimed by the GMCH. The
GMCH issues a shutdown special cycle on the hub interface. This cycle is
retired on the processor bus after it is terminated on the hub interface via
a master abort mechanism.
0000 0010
Flush
This transaction is issued when an agent has invalidated its internal
caches without writing back any modified lines. The GMCH claims this
cycle and retires it.
0000 0011
Halt
This transaction is issued when an agent executes a HLT instruction and
stops program execution. This cycle is claimed by the GMCH and
propagated to the hub interface as a Special Halt Cycle. This cycle is
retired on the processor bus after it is terminated on the hub interface via
a master abort mechanism.
0000 0100
Sync
This transaction is issued when an agent has written back all modified
lines and has invalidated its internal caches. The GMCH claims this cycle
and retires it.
0000 0101
Flush Acknowledge
This transaction is issued when an agent has completed a cache sync
and flush operation in response to an earlier FLUSH# signal assertion.
The GMCH claims this cycle and retires it.
0000 0110
Stop Clock
Acknowledge
This transaction is issued when an agent enters Stop Clock mode. This
cycle is claimed by the GMCH and propagated to the hub interface as a
Special Stop Grant Cycle. This cycle is completed on the processor bus
after it is terminated on the hub interface via a master abort mechanism.
0000 0111
SMI Acknowledge
This transaction is first issued when an agent enters the System
Management Mode (SMM). Ab[7]# is also set at this entry point. All
subsequent transactions from the processor with Ab[7]# set are treated
by the GMCH as accesses to the SMM space. No corresponding cycle is
propagated to the hub interface. To exit the System Management Mode
the processor issues another one of these cycles with the Ab[7]# bit
deasserted. The SMM space access is closed by the GMCH at this point.
All others
Reserved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| FW82815 S L5NQ | 制造商:Intel 功能描述:Graphics and Memory Controller Hub 544-Pin BGA |
| FW82815EM S L4MP | 制造商:Intel 功能描述:GRAPHICS AND MEMORY CONTROLLER HUB (GMCH2-M) |
| FW82815SL5NQ | 制造商:Intel 功能描述: |
| FW828201CA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| FW82840 S L3TA | 制造商:Intel 功能描述:Memory Controller Hub 544-Pin BGA |
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