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參數(shù)資料
| 型號： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 60/172頁 |
| 文件大?。?/td> | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
60
Datasheet
DOS Area (00000h–9FFFFh)
The DOS area is 640 KB in size is always mapped to the main memory controlled by the GMCH.
Video Buffer Area (A0000h–BFFFFh)
The 128 KB graphics adapter memory region is normally mapped to a legacy video device on the hub
interface/PCI (typically VGA controller). This area is not controlled by attribute bits and processor –
initiated cycles in this region are forwarded to either the hub interface or the AGP/Internal Graphics
Device for termination. This region is also the default region for SMM space.
Accesses to this range are directed to either the hub interface or the AGP/internal Graphics Device based
on the configuration. The configuration is specified by:
1. AGP on/off configuration bit
2. AGP off: GMS bits of the SMRAM register in the GMCH Device 0 configuration space. There is
additional steering information coming from the Device 2* configuration registers and from some
of the VGA registers in the Graphics device.
3. AGP on: GMCHCFG (Device 0, bit 5, PCI-PCI Command) and BCTRL (Device 1, bit 3, PCI-PCI
Bridge Control) configuration registers
Control is applied for accesses initiated from any of the system interfaces; that is, processor bus, the hub
interface, or AGP (if enabled). Note that for the hub interface to AGP/PCI accesses, only memory write
operations are supported. Any AGP/PCI initiated VGA accesses targeting the GMCH will master abort.
For more details, see the descriptions in the configuration registers specified above.
The SMRAM Control register controls how SMM accesses to this space are treated.
Monochrome Adapter (MDA) Range (B0000h–B7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome) in the system.
In an AGP system, accesses in the standard VGA range are forwarded to the AGP bus (depending on
configuration bits). Since the monochrome adapter may be on the hub interface/PCI (or ISA) bus, the
GMCH must decode cycles in the MDA range and forward them to the hub interface. This capability is
controlled by a configuration bit (MDA bit – Device 0, BEh). In addition to the memory range B0000h
to B7FFFh, the GMCH decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3Bah and 3BFh and forwards
them to the hub interface.
In an internal graphics system, the GMS bits of the SMRAM register in Device 0, bits in the Device 2
PCICMD register, and bits from some of the VGA registers control this functionality.
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