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參數(shù)資料
| 型號： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 125/172頁 |
| 文件大小： | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
Datasheet
125
System BIOS Area (F0000h–FFFFFh)
This area is a single 64 KB segment. This segment can be assigned read and write attributes. It is by
default (after reset) read/write disabled and cycles are forwarded to the hub interface. By manipulating
the read/write attributes, the GMCH can “shadow” BIOS into the main DRAM. When disabled, this
segment is not remapped.
4.1.3.
Extended Memory Area
This memory area covers 100000h (1 MB) to FFFFFFFFh (4 GB-1) address range and it is divided into
the following regions:
Main DRAM Memory from 1 MB to the Top of Memory; maximum of 512 MB using 128M
technology
PCI Memory space from the Top of Memory to 4 GB with two specific ranges:
APIC Configuration Space from FEC0_0000h (4 GB-20 MB) to FECF_FFFFh and FEE0
_
0000h to
FEEF
_
FFFFh
High BIOS area from 4 GB to 4 GB–2 MB
Main DRAM Address Range (0010_0000h to Top of Main Memory)
The address range from 1 MB to the top of main memory (TOM) is mapped to main DRAM address
range. The Top of memory is limited to 512 MB. All accesses to addresses within this range will be
forwarded to the DRAM unless a hole in this range is created.
15 MB–16 MB Hole
A hole can be created at 15 MB–16 MB as controlled by the fixed hole enable (FDHC register) in
Device 0 space. Accesses within this hole are forwarded to the hub interface. The range of physical
DRAM memory disabled by opening the hole is not remapped to the Top of the memory – that physical
DRAM space is not accessible. This 15 MB–16 MB hole is an optionally enabled ISA hole. Video
accelerators originally used this hole. It is also used by validation and customer SV teams for some of
their test cards. This is why it is being supported. There is no inherent BIOS request for the 15–16 MB
hole.
Extended SMRAM Address Range (Top of Main Memory–TSEG)
The HSEG and TSEG SMM transaction address spaces reside in this extended memory area.
HSEG
SMM-mode processor accesses to enabled HSEG are remapped to 000A0000h–000BFFFFh. Non-SMM-
mode processor accesses to enabled HSEG are considered invalid are terminated immediately on the
FSB. The exception to this is non-SMM-mode write-back cycles. They are remapped to SMM space to
maintain cache coherency. AGP and hub interface originated cycles to enabled SMM space are not
allowed. Physical DRAM behind the HSEG transaction address is not remapped and is not accessible.
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相關(guān)代理商/技術(shù)參數(shù) |
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| FW82815 S L5NQ | 制造商:Intel 功能描述:Graphics and Memory Controller Hub 544-Pin BGA |
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