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| 型號： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 22/172頁 |
| 文件大小： | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
22
Datasheet
2.1.
Host Interface Signals
Signal Name
Type
Description
CPURST#
O
AGTL+
CPU Reset.
The GMCH asserts CPURST# while RESET# (PCIRST# from the I/O
Controller Hub) is asserted and for approximately 1 ms after RESET# is deasserted.
The GMCH also pulses CPURST# for approximately 1 ms when requested via a
hub interface special cycle. The CPURST# allows the processor to begin execution
in a known state.
HA[31:3]#
I/O
AGTL+
Host Address Bus.
HA[31:3]# connect to the processor address bus. During
processor cycles, HA[31:3]# are inputs. The GMCH drives HA[31:3]# during snoop
cycles on behalf of Primary PCI. Note that the address bus is inverted on the
processor bus.
HD[63:0]#
I/O
AGTL+
Host Data.
These signals are connected to the processor data bus. Note that the
data signals are inverted on the processor bus.
ADS#
I/O
AGTL+
Address Strobe.
The processor bus owner asserts ADS# to indicate the first of two
cycles of a request phase.
BNR#
I/O
AGTL+
Block Next Request.
Used to block the current request bus owner from issuing a
new request. This signal is used to dynamically control the processor bus pipeline
depth.
BPRI#
O
AGTL+
Priority Agent Bus Request.
The GMCH is the only priority agent on the processor
bus. It asserts this signal to obtain the ownership of the address bus. This signal
has priority over symmetric bus requests and will cause the current symmetric
owner to stop issuing new transactions unless the HLOCK# signal was asserted.
DBSY#
I/O
AGTL+
Data Bus Busy.
Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.
DEFER#
O
AGTL+
Defer.
The GMCH will generate a deferred response as defined by the rules of the
GMCH dynamic defer policy. The GMCH will also use the DEFER# signal to
indicate a processor retry response.
DRDY#
I/O
AGTL+
Data Ready.
Asserted for each cycle that data is transferred.
HIT#
I/O
AGTL+
Hit.
Indicates that a caching agent holds an unmodified version of the requested
line. Also driven in conjunction with HITM# by the target to extend the snoop
window.
HITM#
I/O
AGTL+
Hit Modified.
Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line.
HITM# is also driven in conjunction with HIT# to extend the snoop window.
HLOCK#
I
AGTL+
Host Lock.
All processor bus cycles sampled with the assertion of HLOCK# and
ADS#, until the negation of HLOCK# must be atomic (i.e., no hub interface or
GMCH graphics snoopable access to SDRAM is allowed when HLOCK# is asserted
by the processor).
HREQ[4:0]#
I/O
AGTL+
Host Request Command.
Asserted during both clocks of request phase. In the first
clock, the signals define the transaction type to a level of detail that is sufficient to
begin a snoop request. In the second clock, the signals carry additional information
to define the complete transaction type.
The transactions supported by the GMCH are defined in the Host Interface section
of this document.
HTRDY#
I/O
AGTL+
Host Target Ready.
Indicates that the target of the processor transaction is able to
enter the data transfer phase.
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