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| 型號(hào)： | FW82815 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 67/172頁(yè) |
| 文件大?。?/td> | 795K |
| 代理商： | FW82815 |
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82815 GMCH
R
Datasheet
67
Bit
Description
15:8
Next Capability Pointer—RO.
This field has two possible values based on APCONT[0] at offset 51h:
A0h when APCONT[0] = 0 (AGP Mode) meaning the next capability pointer is ACAPID.
00h when APCONT[0] = 1 (GFX Mode) meaning that this was the last capability pointer in the list.
7:0
CAP_ID—RO.
This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for
vendor dependent capability pointers.
3.4.24.
BUFF_SC—System Memory Buffer Strength Control Register
(Device 0)
Address Offset:
92–93h
Default Value:
FFFFh
Access:
Read/Write
Size:
16 bits
This register programs the system memory DRAM interface signal buffer strengths, with the exception of
the CKEs. The programming of these bits should be based on DRAM density (x8 or x16), DRAM
technology (16Mb, 64Mb, 128Mb or 256 Mb), rows populated, etc.. Note that x4 & x32 DRAMs are not
supported. Registered DIMMs and DIMMS with ECC are also not supported and BIOS upon detection
of ECC via SPD, should report to the user that ECC DIMM timings are not supported by the GMCH.
In the descriptions below, the term “Row” is equivalent to one side of one DIMM. In other words, a
“single-sided” DIMM contains one populated row (always an odd numbered), and one empty row (even
numbered). A “double-sided” DIMM contains two populated rows.
All buffer strengths are based on the number of “l(fā)oads” connected to each pin of a given signal group. A
“l(fā)oad” represents one pin of one SDRAM Device. The GMCH pin is implied and not counted in the load
equations. The number of loads on a given signal for a given configuration can be determined entirely
from the width of the SDRAM devices that populate each row in the configuration. This information is
readily available for each row via the Serial Presence Detect mechanism.
15
14
13
12
11
10
9
8
SCS[5]#
Buffer
Strength
SCS[4]#
Buffer
Strength
SCS[3]#
Buffer
Strength
SCS[2]#
Buffer
Strength
SCS[1]#
Buffer
Strength
SCS[0]#
Buffer
Strength
SMAC[7:4]# Buffer
Strength
7
6
5
4
3
2
1
0
SMAB[7:4]# Buffer
Strength
SMAA[7:4] Buffer
Strength
MD and DQM Buffer
Strengths
Control Buffer Strengths
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