
Samsung ASIC
5-219
STD130
SPARAM_LP
Low-Power Single-Port Asynchronous Static RAM
Application Notes
1.
Permitting over-the-cell routing.
In chip-level layout, over-the-cell routing in SPARAM_LP is permitted for both Metal-5 and Metal-6
layers.
2.
Incoming power bus should be adjusted to guarantee NOT more than 10% voltage drop at typical-case
current levels.
3.
Power stripe should be tapped from both sides of SPARAM_LP.
4.
Avoiding short transition on the address bus.
In SPARAM_LP, rather than the write operation which is synchronously performed by WEN signal, the
read operation is asynchronously performed whenever the address transition is occurred. In this case, if
the short transition on the address, called a skew, is happened, since SPARAM_LP recognizes the short
address transition as the stable address transition and do perform a read operation. At that time, while
in the read operation, the data stored in the memory may be corrupted due to the short transition. To
prevent such fail, the stable address cycle time(tcyc) is required. The essential requirement to recognize
valid address transition is that at least minimum address period should be equal or greater than tacc
(access time).
5.
Power reduction during standby mode.
The standby power is measured on the condition that only CSN is disable mode and other signals are in
operation mode except that OEN is tied to low. If any of signals are activated while in standby mode, the
power will be consumed because the input switching activities are occurred by the signal transition.
Therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in
standby mode. standby mode.