
Samsung ASIC
4-115
STD130
PvSCKDSby
Schmitt Trigger Level Input Clock Driver
Switching Characteristics
PHSCKDSD2
(Typical process, 25
°
C, 1.8V, 3.3V, t
R
/t
F
 = 1.50ns, SL: Standard Load)
PHSCKDSD4
PHSCKDSD6
PHSCKDSD8
Path
Parameter
Delay [ns]
 SL = 2
0.124
0.104
0.930
1.394
 < 
Delay Equations [ns]
Group1*
0.120 + 0.002*SL
0.101 + 0.002*SL
0.928 + 0.001*SL
1.392 + 0.001*SL
Group2*
0.109 + 0.002*SL
0.094 + 0.002*SL
0.933 + 0.001*SL
1.400 + 0.001*SL
Group3*
0.102 + 0.002*SL
0.088 + 0.002*SL
0.935 + 0.001*SL
1.403 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275,   *Group2 : 275 < 
Path
Parameter
Delay [ns]
 SL = 2
0.184
0.149
1.087
1.567
 < 
Delay Equations [ns]
Group1*
0.182 + 0.001*SL
0.147 + 0.001*SL
1.086 + 0.001*SL
1.566 + 0.001*SL
Group2*
0.167 + 0.001*SL
0.140 + 0.001*SL
1.104 + 0.001*SL
1.583 + 0.001*SL
Group3*
0.153 + 0.001*SL
0.132 + 0.001*SL
1.111 + 0.001*SL
1.591 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549,   *Group2 : 549 < 
Path
Parameter
Delay [ns]
 SL = 2
0.246
0.199
1.233
1.731
 < 
Delay Equations [ns]
Group1*
0.245 + 0.001*SL
0.198 + 0.001*SL
1.232 + 0.000*SL
1.731 + 0.000*SL
Group2*
0.234 + 0.001*SL
0.192 + 0.001*SL
1.264 + 0.000*SL
1.758 + 0.000*SL
Group3*
0.217 + 0.001*SL
0.183 + 0.001*SL
1.279 + 0.000*SL
1.772 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823,   *Group2 : 823 < 
Path
Parameter
Delay [ns]
 SL = 2
0.304
0.251
1.372
1.892
 < 
Delay Equations [ns]
Group1*
0.303 + 0.000*SL
0.250 + 0.000*SL
1.371 + 0.000*SL
1.891 + 0.000*SL
Group2*
0.300 + 0.000*SL
0.247 + 0.000*SL
1.414 + 0.000*SL
1.927 + 0.000*SL
Group3*
0.286 + 0.000*SL
0.238 + 0.000*SL
1.439 + 0.000*SL
1.948 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096,   *Group2 : 1096 <