
Samsung ASIC
4-35
STD130
PvOByz
Normal Output Buffers
Switching Characteristics
(Typical process, 25
°
C, 1.8V, 3.3V, t
R
/t
F
=0.15ns, CL: Capacitive Load[pF])
PHOB1
PHOB2
PHOB4
PHOB8
Path
Parameter
Delay [ns]
 CL = 50.0pF
36.041
26.590
17.517
13.347
 < 
Delay Equations [ns]
Group1*
2.064 + 0.680*CL
1.528 + 0.501*CL
1.550 + 0.319*CL
1.396 + 0.239*CL
Group2*
2.063 + 0.680*CL
1.526 + 0.501*CL
1.553 + 0.319*CL
1.397 + 0.239*CL
Group3*
2.066 + 0.680*CL
1.526 + 0.501*CL
1.550 + 0.319*CL
1.397 + 0.239*CL
A to PAD
tR
tF
tPLH
tPHL
*Group1 : CL < 50,   *Group2 : 50 = 
Path
Parameter
Delay [ns]
 CL = 50.0pF
18.639
14.640
9.263
7.810
 < 
Delay Equations [ns]
Group1*
1.097 + 0.351*CL
0.858 + 0.276*CL
0.978 + 0.166*CL
0.949 + 0.137*CL
Group2*
1.097 + 0.351*CL
0.860 + 0.276*CL
0.978 + 0.166*CL
0.949 + 0.137*CL
Group3*
1.100 + 0.351*CL
0.857 + 0.276*CL
0.976 + 0.166*CL
0.950 + 0.137*CL
A to PAD
tR
tF
tPLH
tPHL
*Group1 : CL < 50,   *Group2 : 50 = 
Path
Parameter
Delay [ns]
 CL = 50.0pF
9.341
8.636
4.957
5.030
 < 
Delay Equations [ns]
Group1*
0.574 + 0.175*CL
0.510 + 0.163*CL
0.814 + 0.083*CL
0.726 + 0.086*CL
Group2*
0.572 + 0.175*CL
0.510 + 0.163*CL
0.814 + 0.083*CL
0.724 + 0.086*CL
Group3*
0.568 + 0.175*CL
0.510 + 0.163*CL
0.814 + 0.083*CL
0.724 + 0.086*CL
A to PAD
tR
tF
tPLH
tPHL
*Group1 : CL < 50,   *Group2 : 50 = 
Path
Parameter
Delay [ns]
 CL = 50.0pF
4.702
4.329
2.935
2.809
 < 
Delay Equations [ns]
Group1*
0.342 + 0.087*CL
0.274 + 0.081*CL
0.863 + 0.041*CL
0.669 + 0.043*CL
Group2*
0.325 + 0.088*CL
0.268 + 0.081*CL
0.863 + 0.041*CL
0.662 + 0.043*CL
Group3*
0.317 + 0.088*CL
0.265 + 0.081*CL
0.864 + 0.041*CL
0.658 + 0.043*CL
A to PAD
tR
tF
tPLH
tPHL
*Group1 : CL < 50,   *Group2 : 50 =