
STD130
4-110
Samsung ASIC
PvSCKDSby
Schmitt Trigger Level Input Clock Driver
Switching Characteristics
PSCKDSU2
(Typical process, 25
°
C, 1.8V, t
R
/t
F
 = 1.50ns, SL: Standard Load)
PSCKDSU4
PSCKDSU6
PSCKDSU8
Path
Parameter
Delay [ns]
 SL = 2
0.113
0.128
0.748
0.636
 < 
Delay Equations [ns]
Group1*
0.110 + 0.002*SL
0.124 + 0.002*SL
0.747 + 0.001*SL
0.634 + 0.001*SL
Group2*
0.097 + 0.002*SL
0.110 + 0.002*SL
0.755 + 0.001*SL
0.645 + 0.001*SL
Group3*
0.086 + 0.002*SL
0.096 + 0.002*SL
0.757 + 0.001*SL
0.649 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275,   *Group2 : 275 < 
Path
Parameter
Delay [ns]
 SL = 2
0.163
0.181
0.919
0.816
 < 
Delay Equations [ns]
Group1*
0.162 + 0.001*SL
0.180 + 0.001*SL
0.919 + 0.000*SL
0.815 + 0.001*SL
Group2*
0.151 + 0.001*SL
0.166 + 0.001*SL
0.937 + 0.000*SL
0.835 + 0.000*SL
Group3*
0.137 + 0.001*SL
0.150 + 0.001*SL
0.945 + 0.000*SL
0.843 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549,   *Group2 : 549 < 
Path
Parameter
Delay [ns]
 SL = 2
0.205
0.226
1.059
0.961
 < 
Delay Equations [ns]
Group1*
0.204 + 0.001*SL
0.225 + 0.001*SL
1.058 + 0.000*SL
0.960 + 0.000*SL
Group2*
0.199 + 0.001*SL
0.217 + 0.001*SL
1.083 + 0.000*SL
0.988 + 0.000*SL
Group3*
0.189 + 0.001*SL
0.204 + 0.001*SL
1.098 + 0.000*SL
1.003 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823,   *Group2 : 823 < 
Path
Parameter
Delay [ns]
 SL = 2
0.246
0.269
1.183
1.087
 < 
Delay Equations [ns]
Group1*
0.245 + 0.000*SL
0.268 + 0.000*SL
1.183 + 0.000*SL
1.086 + 0.000*SL
Group2*
0.248 + 0.000*SL
0.272 + 0.000*SL
1.212 + 0.000*SL
1.123 + 0.000*SL
Group3*
0.242 + 0.000*SL
0.261 + 0.000*SL
1.233 + 0.000*SL
1.144 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096,   *Group2 : 1096 <