
Table of Contents
1.1 Library Description .............................................................................................. 1-1
1.2 Features .............................................................................................................. 1-2
1.3 EDA Support ....................................................................................................... 1-4
1.4 Product Family..................................................................................................... 1-4
1.4.1 Analog Core Cells...................................................................................... 1-4
1.4.2 Standard Logic Cells ................................................................................. 1-8
1.4.3 Compiled Memory ..................................................................................... 1-8
1.4.4 Input/Output Cells...................................................................................... 1-10
1.5 Timings................................................................................................................ 1-13
1.6 Design for Test (DFT) Methodology .................................................................... 1-21
1.7 Maximum Fanouts............................................................................................... 1-24
1.8 Package Capability by Pitch and Lead Count ..................................................... 1-31
1.9 Power Dissipation................................................................................................ 1-32
1.10 V
DD
/V
SS
Rules and Guidelines............................................................................. 1-36
1.11 Crystal Oscillator Considerations........................................................................ 1-43