
Introduction
Samsung ASIC
1-19
STD130
1.5.5
DELAY MODEL
The STD130 cell timing characteristics consist of the following components:
Cell propagation delay from input to output transitions based on input wave-
form slope, fanout and distributed interconnection wire resistances and
capacitances.
Interconnection wire delay.
Timing requirement parameters including set up time, hold time, recovery
time, skew time, and minimum pulse width.
Derating factors for junction temperature, power supply voltage, and process
variation.
To accomplish accurate timing model, a two dimensional table look-up delay
model has been developed. The index variables of this table are input waveform
slope and output load capacitance (Figure 1-12). Samsung's SoC design
methodology supports an n-dimensional table model, even though a two
dimensional model is used.
Figure 1-12.
2-Dimensional Table Delay Model
Table 1-6 shows the propagation delay data for a 2-input NAND cell. The data in
this table are the high-to-low transition delay times from one of the two input pins
to the output pin. The number of points and values of the index variables can
differ for each cell.
Table 1-6.
Table Delay Model Example
\ CAP
SLOPE
0.005
0.020
0.082
0.207
0.394
0.643
0.015
0.155
0.379
0.828
1.500
0.03760
0.05713
0.07293
0.08812
0.09764
0.07381
0.09827
0.12710
0.15996
0.18785
0.22119
0.24463
0.28675
0.36288
0.43539
0.51788
0.54109
0.58086
0.66595
0.79398
0.96168
0.98482
1.02360
1.10480
1.23320
1.55260
1.57570
1.61400
1.69310
1.81670
Propagation
Delay [ns]
Input Waveform
Slope [ns]
Load
Cap [pF]
1.2
1.5
1.0
0.5
1.0
2.0
3.0
0.40.8