
Introduction
1.9 Power Dissipation
Samsung ASIC
1-33
STD130
1.9.3 DYNAMIC (AC) POWER DISSIPATION
When a CMOS logic gate changes state, it draws switching current as a result of charging or discharging a load
capacitance, C
L
. The power associated with the switching current for a node capacitance, C
L
, is
where V
DD
is the power supply voltage.
In addition to the power dissipated by changing the load capacitance, CMOS circuits consume power due to
current flowing from the power supply to ground through the n- and p-channel transistors during switching.
The dynamic power dissipation for an entire chip is difficult to estimate since it depends on the switching activity
of the circuit. Samsung has found that switching activity is about 10% on the average and recommends using this
number in estimating total dynamic power dissipation.
1.9.4 POWER DISSIPATION IN STD130
This section describes the equations used to estimate the power dissipation in STD130. As explained in the
previous section, the total power dissipation (P
TOTAL
) consists of static power dissipation (P
DC
) and dynamic
power dissipation (P
AC
). Samsung’s internal power estimation tool, CubicPower, uses a methodology based on
the following equations.
P
TOTAL
= P
AC
+ P
DC
P
DC
is negligible in case of CMOS logic in general.
The dynamic power dissipation is caused by four components: input buffers (P
AC_INPUT
), output buffers
(P
AC_OUTPUT
), bi-directional buffers (P
AC_BI
), and internal cells (P
AC_INTERNAL
).
P
AC
= P
AC_ INPUT
+ P
AC_OUTPUT
+ P
AC_BI
+ P
AC_INTERNAL
C
L
V
DD
×
2