
Samsung ASIC
4-105
STD130
PvSCKDCby
Input Clock Driver
Switching Characteristics
PHSCKDCD2
(Typical process, 25
°
C, 1.8V, 3.3V, t
R
/t
F
 = 1.50ns, SL: Standard Load)
PHSCKDCD4
PHSCKDCD6
PHSCKDCD8
Path
Parameter
Delay [ns]
 SL = 2
0.124
0.104
0.690
1.019
 < 
Delay Equations [ns]
Group1*
0.120 + 0.002*SL
0.101 + 0.002*SL
0.688 + 0.001*SL
1.017 + 0.001*SL
Group2*
0.109 + 0.002*SL
0.094 + 0.002*SL
0.693 + 0.001*SL
1.025 + 0.001*SL
Group3*
0.101 + 0.002*SL
0.088 + 0.002*SL
0.695 + 0.001*SL
1.028 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275,   *Group2 : 275 < 
Path
Parameter
Delay [ns]
 SL = 2
0.184
0.149
0.848
1.192
 < 
Delay Equations [ns]
Group1*
0.182 + 0.001*SL
0.148 + 0.001*SL
0.847 + 0.001*SL
1.191 + 0.001*SL
Group2*
0.167 + 0.001*SL
0.140 + 0.001*SL
0.864 + 0.001*SL
1.208 + 0.001*SL
Group3*
0.154 + 0.001*SL
0.131 + 0.001*SL
0.871 + 0.001*SL
1.216 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549,   *Group2 : 549 < 
Path
Parameter
Delay [ns]
 SL = 2
0.246
0.199
0.993
1.357
 < 
Delay Equations [ns]
Group1*
0.245 + 0.001*SL
0.198 + 0.001*SL
0.992 + 0.000*SL
1.356 + 0.000*SL
Group2*
0.234 + 0.001*SL
0.193 + 0.001*SL
1.024 + 0.000*SL
1.383 + 0.000*SL
Group3*
0.218 + 0.001*SL
0.183 + 0.001*SL
1.039 + 0.000*SL
1.397 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823,   *Group2 : 823 < 
Path
Parameter
Delay [ns]
 SL = 2
0.304
0.251
1.132
1.517
 < 
Delay Equations [ns]
Group1*
0.304 + 0.000*SL
0.250 + 0.000*SL
1.131 + 0.000*SL
1.516 + 0.000*SL
Group2*
0.300 + 0.000*SL
0.247 + 0.000*SL
1.175 + 0.000*SL
1.552 + 0.000*SL
Group3*
0.286 + 0.000*SL
0.238 + 0.000*SL
1.199 + 0.000*SL
1.573 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096,   *Group2 : 1096 <