
STD130
4-104
Samsung ASIC
PvSCKDCby
Input Clock Driver
Switching Characteristics
PHSCKDC2
(Typical process, 25
°
C, 1.8V, 3.3V, t
R
/t
F
= 1.50ns, SL: Standard Load)
PHSCKDC4
PHSCKDC6
PHSCKDC8
Path
Parameter
Delay [ns]
SL = 2
0.124
0.105
0.665
1.010
<
Delay Equations [ns]
Group1*
0.121 + 0.002*SL
0.101 + 0.002*SL
0.663 + 0.001*SL
1.008 + 0.001*SL
Group2*
0.109 + 0.002*SL
0.094 + 0.002*SL
0.668 + 0.001*SL
1.015 + 0.001*SL
Group3*
0.101 + 0.002*SL
0.088 + 0.002*SL
0.670 + 0.001*SL
1.018 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275, *Group2 : 275 <
Path
Parameter
Delay [ns]
SL = 2
0.184
0.149
0.823
1.183
<
Delay Equations [ns]
Group1*
0.182 + 0.001*SL
0.147 + 0.001*SL
0.822 + 0.001*SL
1.182 + 0.001*SL
Group2*
0.167 + 0.001*SL
0.140 + 0.001*SL
0.839 + 0.001*SL
1.199 + 0.001*SL
Group3*
0.153 + 0.001*SL
0.131 + 0.001*SL
0.846 + 0.001*SL
1.206 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549, *Group2 : 549 <
Path
Parameter
Delay [ns]
SL = 2
0.246
0.200
0.968
1.348
<
Delay Equations [ns]
Group1*
0.244 + 0.001*SL
0.199 + 0.001*SL
0.968 + 0.000*SL
1.347 + 0.000*SL
Group2*
0.234 + 0.001*SL
0.193 + 0.001*SL
0.999 + 0.000*SL
1.373 + 0.000*SL
Group3*
0.218 + 0.001*SL
0.183 + 0.001*SL
1.015 + 0.000*SL
1.388 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823, *Group2 : 823 <
Path
Parameter
Delay [ns]
SL = 2
0.305
0.251
1.107
1.507
<
Delay Equations [ns]
Group1*
0.304 + 0.000*SL
0.250 + 0.000*SL
1.106 + 0.000*SL
1.507 + 0.000*SL
Group2*
0.301 + 0.000*SL
0.247 + 0.000*SL
1.150 + 0.000*SL
1.542 + 0.000*SL
Group3*
0.286 + 0.000*SL
0.238 + 0.000*SL
1.174 + 0.000*SL
1.564 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096, *Group2 : 1096 <