
STD130
4-100
Samsung ASIC
PvSCKDCby
Input Clock Driver
Switching Characteristics
PSCKDCU2
(Typical process, 25
°
C, 1.8V, t
R
/t
F
 = 1.50ns, SL: Standard Load)
PSCKDCU4
PSCKDCU6
PSCKDCU8
Path
Parameter
Delay [ns]
 SL = 2
0.110
0.089
0.370
0.366
 < 
Delay Equations [ns]
Group1*
0.107 + 0.002*SL
0.086 + 0.002*SL
0.368 + 0.001*SL
0.364 + 0.001*SL
Group2*
0.087 + 0.002*SL
0.067 + 0.002*SL
0.371 + 0.001*SL
0.365 + 0.001*SL
Group3*
0.074 + 0.002*SL
0.057 + 0.002*SL
0.370 + 0.001*SL
0.364 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275,   *Group2 : 275 < 
Path
Parameter
Delay [ns]
 SL = 2
0.149
0.119
0.496
0.482
 < 
Delay Equations [ns]
Group1*
0.147 + 0.001*SL
0.117 + 0.001*SL
0.495 + 0.000*SL
0.481 + 0.000*SL
Group2*
0.127 + 0.001*SL
0.097 + 0.001*SL
0.505 + 0.000*SL
0.485 + 0.000*SL
Group3*
0.107 + 0.001*SL
0.079 + 0.001*SL
0.505 + 0.000*SL
0.484 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549,   *Group2 : 549 < 
Path
Parameter
Delay [ns]
 SL = 2
0.185
0.149
0.600
0.577
 < 
Delay Equations [ns]
Group1*
0.184 + 0.001*SL
0.148 + 0.001*SL
0.599 + 0.000*SL
0.577 + 0.000*SL
Group2*
0.162 + 0.001*SL
0.126 + 0.001*SL
0.615 + 0.000*SL
0.586 + 0.000*SL
Group3*
0.143 + 0.001*SL
0.107 + 0.001*SL
0.620 + 0.000*SL
0.588 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823,   *Group2 : 823 < 
Path
Parameter
Delay [ns]
 SL = 2
0.215
0.177
0.691
0.661
 < 
Delay Equations [ns]
Group1*
0.215 + 0.000*SL
0.176 + 0.000*SL
0.690 + 0.000*SL
0.660 + 0.000*SL
Group2*
0.196 + 0.000*SL
0.154 + 0.000*SL
0.712 + 0.000*SL
0.675 + 0.000*SL
Group3*
0.176 + 0.000*SL
0.135 + 0.000*SL
0.721 + 0.000*SL
0.679 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096,   *Group2 : 1096 <