
1.6 Design for Test (DFT) Methodology
Introduction
STD130
1-22
Samsung ASIC
Figure 1-14.
JTAG Test Access Port (TAP) Block Diagram
Functional Block Descriptions
TAP (Test Access Port)
The TAP is a general-purpose port that provides access to many test support functions built into a component
including the test logic. It includes three inputs (TCK -Test Clock Signal; TMS -Test Mode Signal; and TDI -Test
Data Input) and one output (TDO -Test Data Output) required by the test logic. An optional fourth input (TRSTN -
Test Reset) is provided for the asynchronous initialization of the test logic. The values applied at the TMS and TDI
pins are sampled on the rising edge of TCK, and the value placed on TDO changes on the falling edge of TCK.
TAP Controller
The TAP controller receives TCK, interprets the signals on TMS, and generates clock and control signals for both
instruction and test data registers and for other parts of the test circuit as required.
Instruction Register/Instruction Decoder
Test instructions are shifted into and held by the instruction register. Test instructions include tests to be performed
or the test data register addresses to be accessed. A basic 3-bit instruction register and its instruction decoder are
provided as macrofunctions in the library.
Test Data Registers
Test data registers include a bypass register, a boundary scan register, a device identification register and other
design specific registers. Only the bypass and boundary scan registers are mandatory; the rest are optional.
Multiplexer
Scannable
Register
D
R
B
R
I
R
T
C
SYSTEM
LOGIC
Boundary Scan Path
TDI
TMS
TCK
TDO
TEST
ACCESS
PORT
(TAP)
M