
STD130
4-116
Samsung ASIC
PvSCKDSby
Schmitt Trigger Level Input Clock Driver
Switching Characteristics
PHSCKDSU2
(Typical process, 25
°
C, 1.8V, 3.3V, t
R
/t
F
= 1.50ns, SL: Standard Load)
PHSCKDSU4
PHSCKDSU6
PHSCKDSU8
Path
Parameter
Delay [ns]
SL = 2
0.124
0.104
0.922
1.392
<
Delay Equations [ns]
Group1*
0.120 + 0.002*SL
0.101 + 0.002*SL
0.920 + 0.001*SL
1.390 + 0.001*SL
Group2*
0.109 + 0.002*SL
0.094 + 0.002*SL
0.925 + 0.001*SL
1.397 + 0.001*SL
Group3*
0.101 + 0.002*SL
0.088 + 0.002*SL
0.927 + 0.001*SL
1.400 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275, *Group2 : 275 <
Path
Parameter
Delay [ns]
SL = 2
0.183
0.149
1.080
1.565
<
Delay Equations [ns]
Group1*
0.181 + 0.001*SL
0.147 + 0.001*SL
1.079 + 0.001*SL
1.563 + 0.001*SL
Group2*
0.167 + 0.001*SL
0.140 + 0.001*SL
1.097 + 0.001*SL
1.580 + 0.001*SL
Group3*
0.154 + 0.001*SL
0.131 + 0.001*SL
1.104 + 0.001*SL
1.589 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549, *Group2 : 549 <
Path
Parameter
Delay [ns]
SL = 2
0.246
0.200
1.226
1.730
<
Delay Equations [ns]
Group1*
0.244 + 0.001*SL
0.199 + 0.001*SL
1.225 + 0.000*SL
1.729 + 0.000*SL
Group2*
0.234 + 0.001*SL
0.192 + 0.001*SL
1.256 + 0.000*SL
1.755 + 0.000*SL
Group3*
0.217 + 0.001*SL
0.183 + 0.001*SL
1.272 + 0.000*SL
1.770 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823, *Group2 : 823 <
Path
Parameter
Delay [ns]
SL = 2
0.305
0.251
1.364
1.889
<
Delay Equations [ns]
Group1*
0.304 + 0.000*SL
0.250 + 0.000*SL
1.363 + 0.000*SL
1.888 + 0.000*SL
Group2*
0.300 + 0.000*SL
0.247 + 0.000*SL
1.407 + 0.000*SL
1.925 + 0.000*SL
Group3*
0.285 + 0.000*SL
0.238 + 0.000*SL
1.432 + 0.000*SL
1.946 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096, *Group2 : 1096 <