
Samsung ASIC
4-103
STD130
PvSCKDCby
Input Clock Driver
Switching Characteristics
PMSCKDCU2
(Typical process, 25
°
C, 1.8V, 2.5V, t
R
/t
F
= 1.50ns, SL: Standard Load)
PMSCKDCU4
PMSCKDCU6
PMSCKDCU8
Path
Parameter
Delay [ns]
SL = 2
0.121
0.128
0.898
0.938
<
Delay Equations [ns]
Group1*
0.117 + 0.002*SL
0.125 + 0.002*SL
0.896 + 0.001*SL
0.936 + 0.001*SL
Group2*
0.107 + 0.002*SL
0.118 + 0.002*SL
0.901 + 0.001*SL
0.949 + 0.001*SL
Group3*
0.099 + 0.002*SL
0.110 + 0.002*SL
0.902 + 0.001*SL
0.954 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275, *Group2 : 275 <
Path
Parameter
Delay [ns]
SL = 2
0.181
0.202
1.055
1.187
<
Delay Equations [ns]
Group1*
0.179 + 0.001*SL
0.200 + 0.001*SL
1.054 + 0.001*SL
1.186 + 0.001*SL
Group2*
0.164 + 0.001*SL
0.194 + 0.001*SL
1.071 + 0.001*SL
1.213 + 0.001*SL
Group3*
0.151 + 0.001*SL
0.184 + 0.001*SL
1.078 + 0.001*SL
1.227 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549, *Group2 : 549 <
Path
Parameter
Delay [ns]
SL = 2
0.243
0.278
1.201
1.426
<
Delay Equations [ns]
Group1*
0.242 + 0.001*SL
0.277 + 0.001*SL
1.200 + 0.000*SL
1.425 + 0.000*SL
Group2*
0.230 + 0.001*SL
0.275 + 0.001*SL
1.231 + 0.000*SL
1.464 + 0.000*SL
Group3*
0.215 + 0.001*SL
0.267 + 0.001*SL
1.246 + 0.000*SL
1.489 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823, *Group2 : 823 <
Path
Parameter
Delay [ns]
SL = 2
0.301
0.354
1.339
1.658
<
Delay Equations [ns]
Group1*
0.301 + 0.000*SL
0.353 + 0.000*SL
1.339 + 0.000*SL
1.657 + 0.000*SL
Group2*
0.296 + 0.000*SL
0.356 + 0.000*SL
1.381 + 0.000*SL
1.708 + 0.000*SL
Group3*
0.283 + 0.000*SL
0.350 + 0.000*SL
1.406 + 0.000*SL
1.742 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096, *Group2 : 1096 <