
Samsung ASIC
4-101
STD130
PvSCKDCby
Input Clock Driver
Switching Characteristics
PMSCKDC2
(Typical process, 25
°
C, 1.8V, 2.5V, t
R
/t
F
 = 1.50ns, SL: Standard Load)
PMSCKDC4
PMSCKDC6
PMSCKDC8
Path
Parameter
Delay [ns]
 SL = 2
0.121
0.128
0.906
0.924
 < 
Delay Equations [ns]
Group1*
0.117 + 0.002*SL
0.125 + 0.002*SL
0.904 + 0.001*SL
0.922 + 0.001*SL
Group2*
0.107 + 0.002*SL
0.117 + 0.002*SL
0.909 + 0.001*SL
0.934 + 0.001*SL
Group3*
0.099 + 0.002*SL
0.111 + 0.002*SL
0.910 + 0.001*SL
0.939 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275,   *Group2 : 275 < 
Path
Parameter
Delay [ns]
 SL = 2
0.180
0.201
1.064
1.172
 < 
Delay Equations [ns]
Group1*
0.178 + 0.001*SL
0.199 + 0.001*SL
1.062 + 0.001*SL
1.171 + 0.001*SL
Group2*
0.164 + 0.001*SL
0.194 + 0.001*SL
1.079 + 0.001*SL
1.198 + 0.001*SL
Group3*
0.151 + 0.001*SL
0.184 + 0.001*SL
1.086 + 0.001*SL
1.212 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549,   *Group2 : 549 < 
Path
Parameter
Delay [ns]
 SL = 2
0.243
0.278
1.209
1.411
 < 
Delay Equations [ns]
Group1*
0.242 + 0.001*SL
0.277 + 0.001*SL
1.208 + 0.000*SL
1.410 + 0.000*SL
Group2*
0.230 + 0.001*SL
0.275 + 0.001*SL
1.239 + 0.000*SL
1.450 + 0.000*SL
Group3*
0.215 + 0.001*SL
0.267 + 0.001*SL
1.254 + 0.000*SL
1.475 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823,   *Group2 : 823 < 
Path
Parameter
Delay [ns]
 SL = 2
0.302
0.354
1.347
1.643
 < 
Delay Equations [ns]
Group1*
0.301 + 0.000*SL
0.353 + 0.000*SL
1.347 + 0.000*SL
1.642 + 0.000*SL
Group2*
0.297 + 0.000*SL
0.356 + 0.000*SL
1.390 + 0.000*SL
1.693 + 0.000*SL
Group3*
0.282 + 0.000*SL
0.350 + 0.000*SL
1.414 + 0.000*SL
1.727 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096,   *Group2 : 1096 <