
Samsung ASIC
3-71
STD130
OR2B/OR2BD2/OR2BD4/OR2BD8
2-Input OR with one Inverted Input, 1X/2X/4X/8X Drive
Logic Symbol
Cell Data
Switching Characteristics
OR2B
(Typical process, 25
°
C, 1.8V, t
R
/t
F
= 0.15ns, SL: Standard Load)
OR2BD2
Input Load (SL)
OR2BD2
AN
B
0.7
1.1
Gate Count
OR2BD2 OR2BD4 OR2BD8
OR2B
AN
0.6
OR2BD4
AN
0.7
OR2BD8
AN
0.9
OR2B
B
B
B
0.8
1.1
2.2
2.33
2.33
3.00
5.00
Truth Table
AN
B
0
1
0
1
Y
1
1
0
1
0
0
1
1
Y
AN
B
Path
Parameter
Delay [ns]
SL = 2
0.078
0.082
0.164
0.162
0.082
0.083
0.112
0.157
<
Delay Equations [ns]
Group1*
0.037 + 0.021*SL
0.047 + 0.017*SL
0.144 + 0.010*SL
0.138 + 0.012*SL
0.043 + 0.020*SL
0.050 + 0.017*SL
0.091 + 0.010*SL
0.132 + 0.012*SL
Group2*
0.035 + 0.021*SL
0.051 + 0.016*SL
0.146 + 0.010*SL
0.146 + 0.010*SL
0.038 + 0.021*SL
0.050 + 0.016*SL
0.093 + 0.010*SL
0.140 + 0.010*SL
Group3*
0.032 + 0.021*SL
0.049 + 0.017*SL
0.146 + 0.010*SL
0.154 + 0.009*SL
0.033 + 0.021*SL
0.048 + 0.017*SL
0.094 + 0.010*SL
0.148 + 0.009*SL
AN to Y
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
B to Y
*Group1 : SL < 4, *Group2 : =
Path
Parameter
Delay [ns]
SL = 2
0.057
0.065
0.167
0.158
0.060
0.064
0.107
0.149
<
Delay Equations [ns]
Group1*
0.037 + 0.010*SL
0.045 + 0.010*SL
0.155 + 0.006*SL
0.143 + 0.008*SL
0.041 + 0.010*SL
0.045 + 0.009*SL
0.096 + 0.006*SL
0.134 + 0.008*SL
Group2*
0.035 + 0.010*SL
0.051 + 0.008*SL
0.158 + 0.005*SL
0.150 + 0.006*SL
0.039 + 0.010*SL
0.049 + 0.009*SL
0.099 + 0.005*SL
0.141 + 0.006*SL
Group3*
0.030 + 0.011*SL
0.051 + 0.008*SL
0.161 + 0.005*SL
0.162 + 0.005*SL
0.032 + 0.011*SL
0.051 + 0.008*SL
0.102 + 0.005*SL
0.153 + 0.005*SL
AN to Y
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
B to Y
*Group1 : SL < 4, *Group2 : =