
1.5 Timings
Introduction
STD130
1-18
Samsung ASIC
1.5.3 BEST AND WORST CASE CONDITIONS
The following expressions also allow for the effect of process variation on circuit
performance. Best case (Worst case):
T
BC
(T
WC
) = K
P
×
K
T
×
K
V
×
T
NOM
where,
T
BC
(T
WC
)
is the darted timing,
K
P
is the process derating factor,
K
T
is the temperature derating factor,
K
V
is the voltage derating factor,
T
NOM
is the nominal timing
The best and worst case darted timings may be determined by picking the prop-
er values of the derating factors (Table 1-3, Table 1-4 and Table 1-5) Nominal
timing is defined as the timing under the conditions of nominal process, 25
°
C
junction temperature, and 1.8V power supply voltage. Derating factors for
conditions
between those shown in the tables may be determined by linear interpolation.
1.5.4 DERATING FACTORS OF STD130
The multipliers can be applied to nominal delay data in order to estimate the
effects of supply voltage (V
DD
), junction temperature (T
J
), and process. Nominal
data are provided for conditions of V
DD
= 1.8V, T
J
= 25
°
C and typical process.
The junction temperature, T
J
, is calculated using chip power dissipation and the
thermal resistance of the package to the ambient temperature,
θ
JA
(also see
Section. 1.9.5). Information on package thermal performance can be obtained
from your local Samsung Technology Center or Samsung's worldwide
headquarters.
The derating factors for STD130 are as follows in Tables 1-3, Table 1-4 and Table
1-5.
Table 1-3.
STD130 Cell Process Derating Factor (K
P
)
Table 1-4.
Temp. (
o
C)
K
T
STD130 Cell Temperature Derating Factor (K
T
)
125
85
1.124
1.076
1.058
Table 1-5.
Voltage (V)
K
V
STD130 Cell Voltage Derating Factor (K
V
)
1.65
1.087
Process Factor (K
P
)
Slow
1.245
Typ
1.000
Fast
0.813
70
25
0
–40
0.912
1.000
0.967
1.8
1.000
1.95
0.934