
STD130
4-30
Samsung ASIC
PvOByz
Normal Output Buffers
Switching Characteristics
(Typical process, 25
°
C, 1.8V, 2.5V, t
R
/t
F
=0.15ns, CL: Capacitive Load[pF])
PMOB1
PMOB2
PMOB4
PMOB8
Path
Parameter
Delay [ns]
 CL = 50.0pF
26.041
22.781
13.002
12.354
 < 
Delay Equations [ns]
Group1*
1.396 + 0.493*CL
1.211 + 0.431*CL
1.131 + 0.237*CL
1.215 + 0.223*CL
Group2*
1.397 + 0.493*CL
1.213 + 0.431*CL
1.130 + 0.237*CL
1.216 + 0.223*CL
Group3*
1.397 + 0.493*CL
1.213 + 0.431*CL
1.130 + 0.237*CL
1.216 + 0.223*CL
A to PAD
tR
tF
tPLH
tPHL
*Group1 : CL < 50,   *Group2 : 50 = 
Path
Parameter
Delay [ns]
 CL = 50.0pF
13.046
12.985
6.841
7.474
 < 
Delay Equations [ns]
Group1*
0.726 + 0.246*CL
0.697 + 0.246*CL
0.906 + 0.119*CL
0.876 + 0.132*CL
Group2*
0.724 + 0.246*CL
0.695 + 0.246*CL
0.906 + 0.119*CL
0.874 + 0.132*CL
Group3*
0.724 + 0.246*CL
0.695 + 0.246*CL
0.907 + 0.119*CL
0.877 + 0.132*CL
A to PAD
tR
tF
tPLH
tPHL
*Group1 : CL < 50,   *Group2 : 50 = 
Path
Parameter
Delay [ns]
 CL = 50.0pF
6.558
6.505
3.910
4.063
 < 
Delay Equations [ns]
Group1*
0.414 + 0.123*CL
0.367 + 0.123*CL
0.941 + 0.059*CL
0.773 + 0.066*CL
Group2*
0.401 + 0.123*CL
0.362 + 0.123*CL
0.942 + 0.059*CL
0.768 + 0.066*CL
Group3*
0.397 + 0.123*CL
0.359 + 0.123*CL
0.942 + 0.059*CL
0.764 + 0.066*CL
A to PAD
tR
tF
tPLH
tPHL
*Group1 : CL < 50,   *Group2 : 50 = 
Path
Parameter
Delay [ns]
 CL = 50.0pF
3.398
3.298
2.735
2.506
 < 
Delay Equations [ns]
Group1*
0.426 + 0.059*CL
0.314 + 0.060*CL
1.236 + 0.030*CL
0.906 + 0.032*CL
Group2*
0.375 + 0.060*CL
0.258 + 0.061*CL
1.249 + 0.030*CL
0.882 + 0.032*CL
Group3*
0.335 + 0.061*CL
0.222 + 0.061*CL
1.251 + 0.030*CL
0.866 + 0.033*CL
A to PAD
tR
tF
tPLH
tPHL
*Group1 : CL < 50,   *Group2 : 50 =