
STD130
5-74
Samsung ASIC
SPARAM_HD
High-Density Single-Port Asynchronous Static RAM
Application Notes
1.
Permitting over-the-cell routing
In chip-level layout, over-the-cell routing in SPARAM_HD is permitted for only Metal-5 and Metal-6
layers.
2.
Incoming power bus should be adjusted to guarantee NOT more than 10% voltage drop at typical-case
current levels.
3.
Power stripe should be tapped from both sides of SPARAM_HD.
4.
Avoiding short transition on the address bus
In SPARAM_HD, rather than the write operation which is synchronously performed by WEN signal, the
read operation is asynchronously performed whenever the address transition is occurred. In this case, if
the short transition on the address, called a skew, is happened, since SPARAM_HD recognizes the
short address transition as the stable address transition and do perform a read operation. At that time,
while in the read operation, the data stored in the memory may be corrupted due to the short transition.
To prevent such fail, the stable address cycle time (tcyc) is required. The essential requirement to
recognize valid address transition is that at least minimum address period should be equal or greater
than tacc (access time).
5.
Power reduction during standby mode.
The standby power is measured on the condition that only CSN is in disable mode and other signals are
in operation mode except that OEN is tied to low. If any of signals are activated while in standby mode,
the power will be consumed because the input switching activities are occurred by the signal transition.
Therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in
standby mode.
<2-bank architecture >
RAM Core
W
D
X
W
D
RAM Core
Y-Dec &
Sense Amp.
Control Block
Y-Dec &
Sense Amp.
Y-Dec &
Sense Amp.
Control Block
Y-Dec &
Sense Amp.
RAM Core
W
D
X
W
D
RAM Core
I/O Driver
Address &
Clock Buffers
I/O Driver
VDD
VSS
VDD
VSS
VSS
VDD
VDD
VSS
VDD
VSS
VSS
VDD
A
W
O
C
D
D
D
D