
STD130
4-114
Samsung ASIC
PvSCKDSby
Schmitt Trigger Level Input Clock Driver
Switching Characteristics
PHSCKDS2
(Typical process, 25
°
C, 1.8V, 3.3V, t
R
/t
F
 = 1.50ns, SL: Standard Load)
PHSCKDS4
PHSCKDS6
PHSCKDS8
Path
Parameter
Delay [ns]
 SL = 2
0.124
0.104
0.916
1.364
 < 
Delay Equations [ns]
Group1*
0.120 + 0.002*SL
0.101 + 0.002*SL
0.914 + 0.001*SL
1.362 + 0.001*SL
Group2*
0.109 + 0.002*SL
0.093 + 0.002*SL
0.919 + 0.001*SL
1.370 + 0.001*SL
Group3*
0.101 + 0.002*SL
0.088 + 0.002*SL
0.921 + 0.001*SL
1.373 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275,   *Group2 : 275 < 
Path
Parameter
Delay [ns]
 SL = 2
0.184
0.149
1.074
1.537
 < 
Delay Equations [ns]
Group1*
0.182 + 0.001*SL
0.148 + 0.001*SL
1.073 + 0.001*SL
1.536 + 0.001*SL
Group2*
0.167 + 0.001*SL
0.140 + 0.001*SL
1.090 + 0.001*SL
1.553 + 0.001*SL
Group3*
0.154 + 0.001*SL
0.131 + 0.001*SL
1.097 + 0.001*SL
1.561 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549,   *Group2 : 549 < 
Path
Parameter
Delay [ns]
 SL = 2
0.246
0.200
1.220
1.702
 < 
Delay Equations [ns]
Group1*
0.245 + 0.001*SL
0.198 + 0.001*SL
1.219 + 0.000*SL
1.701 + 0.000*SL
Group2*
0.233 + 0.001*SL
0.193 + 0.001*SL
1.250 + 0.000*SL
1.728 + 0.000*SL
Group3*
0.218 + 0.001*SL
0.183 + 0.001*SL
1.266 + 0.000*SL
1.743 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823,   *Group2 : 823 < 
Path
Parameter
Delay [ns]
 SL = 2
0.305
0.251
1.358
1.862
 < 
Delay Equations [ns]
Group1*
0.304 + 0.000*SL
0.250 + 0.000*SL
1.357 + 0.000*SL
1.861 + 0.000*SL
Group2*
0.300 + 0.000*SL
0.247 + 0.000*SL
1.401 + 0.000*SL
1.897 + 0.000*SL
Group3*
0.286 + 0.000*SL
0.238 + 0.000*SL
1.426 + 0.000*SL
1.918 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096,   *Group2 : 1096 <