
STD130
4-102
Samsung ASIC
PvSCKDCby
Input Clock Driver
Switching Characteristics
PMSCKDCD2
(Typical process, 25
°
C, 1.8V, 2.5V, t
R
/t
F
 = 1.50ns, SL: Standard Load)
PMSCKDCD4
PMSCKDCD6
PMSCKDCD8
Path
Parameter
Delay [ns]
 SL = 2
0.121
0.129
0.922
0.921
 < 
Delay Equations [ns]
Group1*
0.117 + 0.002*SL
0.125 + 0.002*SL
0.920 + 0.001*SL
0.918 + 0.001*SL
Group2*
0.107 + 0.002*SL
0.118 + 0.002*SL
0.925 + 0.001*SL
0.931 + 0.001*SL
Group3*
0.098 + 0.002*SL
0.111 + 0.002*SL
0.927 + 0.001*SL
0.936 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275,   *Group2 : 275 < 
Path
Parameter
Delay [ns]
 SL = 2
0.180
0.202
1.080
1.169
 < 
Delay Equations [ns]
Group1*
0.178 + 0.001*SL
0.200 + 0.001*SL
1.079 + 0.001*SL
1.168 + 0.001*SL
Group2*
0.164 + 0.001*SL
0.194 + 0.001*SL
1.095 + 0.001*SL
1.195 + 0.001*SL
Group3*
0.151 + 0.001*SL
0.184 + 0.001*SL
1.102 + 0.001*SL
1.209 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549,   *Group2 : 549 < 
Path
Parameter
Delay [ns]
 SL = 2
0.243
0.278
1.225
1.408
 < 
Delay Equations [ns]
Group1*
0.242 + 0.001*SL
0.277 + 0.001*SL
1.225 + 0.000*SL
1.407 + 0.000*SL
Group2*
0.230 + 0.001*SL
0.275 + 0.001*SL
1.255 + 0.000*SL
1.447 + 0.000*SL
Group3*
0.215 + 0.001*SL
0.267 + 0.001*SL
1.270 + 0.000*SL
1.472 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823,   *Group2 : 823 < 
Path
Parameter
Delay [ns]
 SL = 2
0.302
0.354
1.363
1.640
 < 
Delay Equations [ns]
Group1*
0.301 + 0.000*SL
0.353 + 0.000*SL
1.363 + 0.000*SL
1.640 + 0.000*SL
Group2*
0.296 + 0.000*SL
0.356 + 0.000*SL
1.406 + 0.000*SL
1.690 + 0.000*SL
Group3*
0.283 + 0.000*SL
0.351 + 0.000*SL
1.430 + 0.000*SL
1.724 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096,   *Group2 : 1096 <