
Samsung ASIC
4-109
STD130
PvSCKDSby
Schmitt Trigger Level Input Clock Driver
Switching Characteristics
PSCKDSD2
(Typical process, 25
°
C, 1.8V, t
R
/t
F
 = 1.50ns, SL: Standard Load)
PSCKDSD4
PSCKDSD6
PSCKDSD8
Path
Parameter
Delay [ns]
 SL = 2
0.112
0.129
0.696
0.665
 < 
Delay Equations [ns]
Group1*
0.109 + 0.002*SL
0.126 + 0.002*SL
0.694 + 0.001*SL
0.663 + 0.001*SL
Group2*
0.094 + 0.002*SL
0.110 + 0.002*SL
0.702 + 0.001*SL
0.674 + 0.001*SL
Group3*
0.083 + 0.002*SL
0.096 + 0.002*SL
0.704 + 0.001*SL
0.678 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275,   *Group2 : 275 < 
Path
Parameter
Delay [ns]
 SL = 2
0.159
0.182
0.857
0.853
 < 
Delay Equations [ns]
Group1*
0.158 + 0.001*SL
0.181 + 0.001*SL
0.856 + 0.000*SL
0.852 + 0.001*SL
Group2*
0.147 + 0.001*SL
0.167 + 0.001*SL
0.874 + 0.000*SL
0.872 + 0.000*SL
Group3*
0.134 + 0.001*SL
0.151 + 0.001*SL
0.881 + 0.000*SL
0.880 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549,   *Group2 : 549 < 
Path
Parameter
Delay [ns]
 SL = 2
0.199
0.228
0.988
1.003
 < 
Delay Equations [ns]
Group1*
0.197 + 0.001*SL
0.227 + 0.001*SL
0.987 + 0.000*SL
1.002 + 0.000*SL
Group2*
0.195 + 0.001*SL
0.219 + 0.001*SL
1.012 + 0.000*SL
1.031 + 0.000*SL
Group3*
0.185 + 0.001*SL
0.204 + 0.001*SL
1.027 + 0.000*SL
1.045 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823,   *Group2 : 823 < 
Path
Parameter
Delay [ns]
 SL = 2
0.241
0.272
1.106
1.133
 < 
Delay Equations [ns]
Group1*
0.240 + 0.000*SL
0.271 + 0.000*SL
1.106 + 0.000*SL
1.133 + 0.000*SL
Group2*
0.245 + 0.000*SL
0.273 + 0.000*SL
1.136 + 0.000*SL
1.169 + 0.000*SL
Group3*
0.239 + 0.000*SL
0.261 + 0.000*SL
1.156 + 0.000*SL
1.191 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096,   *Group2 : 1096 <