
STD130
4-108
Samsung ASIC
PvSCKDSby
Schmitt Trigger Level Input Clock Driver
Switching Characteristics
PSCKDS2
(Typical process, 25
°
C, 1.8V, t
R
/t
F
 = 1.50ns, SL: Standard Load)
PSCKDS4
PSCKDS6
PSCKDS8
Path
Parameter
Delay [ns]
 SL = 2
0.110
0.126
0.692
0.617
 < 
Delay Equations [ns]
Group1*
0.107 + 0.002*SL
0.123 + 0.002*SL
0.690 + 0.001*SL
0.615 + 0.001*SL
Group2*
0.093 + 0.002*SL
0.110 + 0.002*SL
0.698 + 0.001*SL
0.626 + 0.001*SL
Group3*
0.083 + 0.002*SL
0.096 + 0.002*SL
0.701 + 0.001*SL
0.630 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275,   *Group2 : 275 < 
Path
Parameter
Delay [ns]
 SL = 2
0.157
0.181
0.854
0.799
 < 
Delay Equations [ns]
Group1*
0.156 + 0.001*SL
0.179 + 0.001*SL
0.853 + 0.000*SL
0.798 + 0.001*SL
Group2*
0.145 + 0.001*SL
0.166 + 0.001*SL
0.870 + 0.000*SL
0.818 + 0.000*SL
Group3*
0.133 + 0.001*SL
0.149 + 0.001*SL
0.878 + 0.000*SL
0.826 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549,   *Group2 : 549 < 
Path
Parameter
Delay [ns]
 SL = 2
0.197
0.225
0.985
0.944
 < 
Delay Equations [ns]
Group1*
0.196 + 0.001*SL
0.224 + 0.001*SL
0.984 + 0.000*SL
0.943 + 0.000*SL
Group2*
0.193 + 0.001*SL
0.216 + 0.001*SL
1.009 + 0.000*SL
0.972 + 0.000*SL
Group3*
0.183 + 0.001*SL
0.202 + 0.001*SL
1.023 + 0.000*SL
0.986 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823,   *Group2 : 823 < 
Path
Parameter
Delay [ns]
 SL = 2
0.239
0.268
1.103
1.071
 < 
Delay Equations [ns]
Group1*
0.238 + 0.000*SL
0.267 + 0.000*SL
1.103 + 0.000*SL
1.070 + 0.000*SL
Group2*
0.242 + 0.000*SL
0.269 + 0.000*SL
1.132 + 0.000*SL
1.106 + 0.000*SL
Group3*
0.236 + 0.000*SL
0.258 + 0.000*SL
1.153 + 0.000*SL
1.128 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096,   *Group2 : 1096 <