
Samsung ASIC
3-325
STD130
FA/FAD2
Full Adder with 1X/2X Drive
Logic Symbol
Cell Data
Switching Characteristics
FA
(Typical process, 25
°
C, 1.8V, t
R
/t
F
= 0.15ns, SL: Standard Load)
Input Load (SL)
Gate Count
FA
FA
A
1.0
FAD2
A
1.0
FAD2
CI
1.0
B
CI
1.1
B
1.1
1.1
9.00
9.67
CI
A
B
S
CO
Path
Parameter
Delay [ns]
SL = 2
0.096
0.087
0.280
0.297
0.096
0.088
0.330
0.354
0.093
0.091
0.235
0.228
0.095
0.087
0.276
0.292
0.114
0.107
0.326
0.356
0.093
0.091
0.166
0.177
<
Delay Equations [ns]
Group1*
0.057 + 0.019*SL
0.054 + 0.017*SL
0.257 + 0.012*SL
0.271 + 0.013*SL
0.056 + 0.020*SL
0.054 + 0.017*SL
0.306 + 0.012*SL
0.328 + 0.013*SL
0.053 + 0.020*SL
0.058 + 0.017*SL
0.211 + 0.012*SL
0.202 + 0.013*SL
0.055 + 0.020*SL
0.052 + 0.017*SL
0.253 + 0.012*SL
0.266 + 0.013*SL
0.078 + 0.018*SL
0.079 + 0.014*SL
0.303 + 0.012*SL
0.330 + 0.013*SL
0.052 + 0.020*SL
0.056 + 0.017*SL
0.142 + 0.012*SL
0.150 + 0.013*SL
Group2*
0.053 + 0.020*SL
0.056 + 0.016*SL
0.263 + 0.010*SL
0.280 + 0.011*SL
0.055 + 0.020*SL
0.058 + 0.016*SL
0.313 + 0.010*SL
0.337 + 0.011*SL
0.052 + 0.020*SL
0.061 + 0.016*SL
0.218 + 0.010*SL
0.212 + 0.011*SL
0.053 + 0.020*SL
0.055 + 0.017*SL
0.258 + 0.010*SL
0.275 + 0.011*SL
0.072 + 0.019*SL
0.075 + 0.015*SL
0.309 + 0.010*SL
0.339 + 0.011*SL
0.052 + 0.020*SL
0.061 + 0.016*SL
0.148 + 0.010*SL
0.160 + 0.011*SL
Group3*
0.047 + 0.021*SL
0.052 + 0.017*SL
0.268 + 0.010*SL
0.289 + 0.010*SL
0.049 + 0.021*SL
0.055 + 0.016*SL
0.317 + 0.010*SL
0.346 + 0.010*SL
0.046 + 0.021*SL
0.058 + 0.016*SL
0.222 + 0.010*SL
0.221 + 0.010*SL
0.047 + 0.021*SL
0.055 + 0.017*SL
0.263 + 0.010*SL
0.284 + 0.010*SL
0.062 + 0.020*SL
0.066 + 0.016*SL
0.314 + 0.010*SL
0.349 + 0.010*SL
0.047 + 0.021*SL
0.060 + 0.016*SL
0.152 + 0.010*SL
0.171 + 0.010*SL
A to S
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
B to S
CI to S
A to CO
B to CO
CI to CO
*Group1 : SL < 4, *Group2 : =
Truth Table
CI
0
1
0
1
0
1
0
1
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
S
0
1
1
0
1
0
0
1
CO
0
0
0
1
0
1
1
1