
V
MSUNG
S
ELECTRONICS
2
STD130
Samsung ASIC
Analog Cores
Ultra low voltage analog cores : 1.8V
High Resolution analog cores : 3.3V
Digital Cores
Memory Compiler
Fully compilable application specific SRAM
High-density(HD) and low-power(LP)
Single-port(1RW, 1R), dual-port(2RW),
multi-port(1R1W~2R2W)
Duty-free cycle and zero hold time in
synchronous
Bit-write feature available
2-bank architecture
Up to 1M-bit high-capacity repairable SRAM
with redundancy
X : Not Support
Analog
Cores
Bit
Supply Voltage
3.3V
±
5%
1.8V
±
5%
ADC
8
- 125MHz
- 250KHz
10
-
- 30MHz
12
- 250KHz
- 10MHz
-
DAC
10
-
- 80MHz
12
- 2MHz
- 300MHz
-
CODEC
14
- 8K~11KHz
(2.5V)
-
PLL
- 25~300MHz(FS)
- 100~500MHz(FS)
- 200MHz(SSCG)
Application
Hard macro
Soft macro
CPU cores
- ARM7TDMI
- ARM9TDMI
- ARM940T
- ARM920T
AMBA, AHB Wrapper
DSP cores
- Teaklite
- Teak
-
Interface
cores
-
USB1.1, USB2.0, IrDA
UART(16C450,16C550)
IEEE1284,
P1394a LINK
Communica-
tion cores
-
10/100 Ethernet MAC
Decoder
-
RS Decoder,
Viterbi Decoder
Samsung ASIC Macros
Name
Availa-
bility
HD
Description
LP
SPSRAM
O
O
- Single Port Synchronous
static RAM
- up to 512K bits
- SPSRAM with Bit-Write
- up to 512K bits
- SPSRAM with Redundancy
- up to 1M bits
- Dual Port Synchronous static
RAM
- up to 256K bits
- DPSRAM with Bit-Write
- up to 256K bits
- Single Port Asynchronous
static RAM
- up to 512K bits
- SPARAM with Bit-Write
- up to 512K bits
- Synchronous Diffusion pro-
grammable ROM
- up to 512K bits
- synchronous Metal-2 pro-
grammable ROM
- up to 512K bits
- multi-port Asynchronous
Register File RAM
- 1-to-2 write ports, 1-to-2 read
ports
- up to 16K bits
- synchronous First-In First-Out
memory
- up to 64K bits
- synchronous Content
Addressable Memory
- up to 32K bits
SPSRAMBW
O
O
SPSRAMR
O
X
DPSRAM
O
O
DPSRAMBW
O
O
SPARAM
O
O
SPARAMBW
O
O
DROM
O
X
MROM
O
X
ARFRAM
O
X
FIFO
O
X
CAM
O
X