
Samsung ASIC
3-323
STD130
CK2/CK4/CK6/CK8
Internal Clock Driver CMOS 2/4/6/8mA
Switching Characteristics
CK2
(Typical process, 25
°
C, 1.8V, t
R
/t
F
= 0.15ns, SL: Standard Load)
CK4
CK6
CK8
Path
Parameter
Delay [ns]
SL = 2
0.033
0.028
0.088
0.088
<
Delay Equations [ns]
Group1*
0.029 + 0.002*SL
0.025 + 0.002*SL
0.087 + 0.001*SL
0.086 + 0.001*SL
Group2*
0.027 + 0.002*SL
0.023 + 0.002*SL
0.086 + 0.001*SL
0.086 + 0.001*SL
Group3*
0.026 + 0.002*SL
0.022 + 0.002*SL
0.087 + 0.001*SL
0.087 + 0.001*SL
A to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275, *Group2 : 275 <
Path
Parameter
Delay [ns]
SL = 2
0.036
0.031
0.110
0.107
<
Delay Equations [ns]
Group1*
0.035 + 0.001*SL
0.030 + 0.001*SL
0.109 + 0.000*SL
0.106 + 0.000*SL
Group2*
0.030 + 0.001*SL
0.026 + 0.001*SL
0.109 + 0.000*SL
0.106 + 0.000*SL
Group3*
0.029 + 0.001*SL
0.024 + 0.001*SL
0.109 + 0.000*SL
0.106 + 0.000*SL
A to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549, *Group2 : 549 <
Path
Parameter
Delay [ns]
SL = 2
0.033
0.028
0.099
0.097
<
Delay Equations [ns]
Group1*
0.031 + 0.001*SL
0.026 + 0.001*SL
0.098 + 0.000*SL
0.096 + 0.000*SL
Group2*
0.028 + 0.001*SL
0.024 + 0.001*SL
0.098 + 0.000*SL
0.097 + 0.000*SL
Group3*
0.027 + 0.001*SL
0.023 + 0.001*SL
0.098 + 0.000*SL
0.097 + 0.000*SL
A to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823, *Group2 : 823 <
Path
Parameter
Delay [ns]
SL = 2
0.035
0.030
0.110
0.106
<
Delay Equations [ns]
Group1*
0.034 + 0.000*SL
0.030 + 0.000*SL
0.109 + 0.000*SL
0.106 + 0.000*SL
Group2*
0.030 + 0.000*SL
0.026 + 0.000*SL
0.109 + 0.000*SL
0.106 + 0.000*SL
Group3*
0.029 + 0.000*SL
0.024 + 0.000*SL
0.109 + 0.000*SL
0.106 + 0.000*SL
A to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096, *Group2 : 1096 <