
Samsung ASIC
4-25
STD130
PvOByz
Normal Output Buffers
Switching Characteristics
POB1
(Typical process, 25
°
C, 1.8V, t
R
/t
F
=0.15ns, CL: Capacitive Load[pF])
POB2
POB4
POB8
Path
Parameter
Delay [ns]
CL = 50.0pF
29.116
23.158
13.423
11.556
<
Delay Equations [ns]
Group1*
2.086 + 0.541*CL
1.698 + 0.429*CL
1.139 + 0.246*CL
1.265 + 0.206*CL
Group2*
2.084 + 0.541*CL
1.700 + 0.429*CL
1.139 + 0.246*CL
1.268 + 0.206*CL
Group3*
2.087 + 0.541*CL
1.700 + 0.429*CL
1.142 + 0.246*CL
1.265 + 0.206*CL
A to PAD
tR
tF
tPLH
tPHL
*Group1 : CL < 50, *Group2 : 50 =
Path
Parameter
Delay [ns]
CL = 50.0pF
14.893
12.400
6.834
6.376
<
Delay Equations [ns]
Group1*
1.096 + 0.276*CL
0.926 + 0.229*CL
0.604 + 0.125*CL
0.726 + 0.113*CL
Group2*
1.095 + 0.276*CL
0.924 + 0.230*CL
0.604 + 0.125*CL
0.726 + 0.113*CL
Group3*
1.095 + 0.276*CL
0.921 + 0.230*CL
0.604 + 0.125*CL
0.725 + 0.113*CL
A to PAD
tR
tF
tPLH
tPHL
*Group1 : CL < 50, *Group2 : 50 =
Path
Parameter
Delay [ns]
CL = 50.0pF
7.463
6.983
3.516
3.777
<
Delay Equations [ns]
Group1*
0.566 + 0.138*CL
0.525 + 0.129*CL
0.401 + 0.062*CL
0.457 + 0.066*CL
Group2*
0.564 + 0.138*CL
0.522 + 0.129*CL
0.401 + 0.062*CL
0.457 + 0.066*CL
Group3*
0.565 + 0.138*CL
0.520 + 0.129*CL
0.401 + 0.062*CL
0.457 + 0.066*CL
A to PAD
tR
tF
tPLH
tPHL
*Group1 : CL < 50, *Group2 : 50 =
Path
Parameter
Delay [ns]
CL = 50.0pF
3.750
3.512
1.930
2.075
<
Delay Equations [ns]
Group1*
0.308 + 0.069*CL
0.298 + 0.064*CL
0.372 + 0.031*CL
0.419 + 0.033*CL
Group2*
0.303 + 0.069*CL
0.287 + 0.064*CL
0.372 + 0.031*CL
0.417 + 0.033*CL
Group3*
0.300 + 0.069*CL
0.282 + 0.065*CL
0.372 + 0.031*CL
0.415 + 0.033*CL
A to PAD
tR
tF
tPLH
tPHL
*Group1 : CL < 50, *Group2 : 50 =