
Samsung ASIC
3-69
STD130
OR2/OR2D2/OR2D4/OR2D8
2-Input OR with 1X/2X/4X/8X Drive
Logic Symbol
Cell Data
Switching Characteristics
OR2
(Typical process, 25
°
C, 1.8V, t
R
/t
F
= 0.15ns, SL: Standard Load)
OR2D2
Input Load (SL)
OR2D2
A
B
1.0
1.1
Gate Count
OR2D2 OR2D4 OR2D8
OR2
OR2D4
A
1.0
OR2D8
A
2.0
OR2
A
B
B
B
0.8
0.8
1.1
2.1
1.67
1.67
2.33
4.33
Y
A
B
Path
Parameter
Delay [ns]
SL = 2
0.082
0.083
0.100
0.152
0.087
0.085
0.113
0.158
<
Delay Equations [ns]
Group1*
0.042 + 0.020*SL
0.048 + 0.018*SL
0.079 + 0.010*SL
0.127 + 0.012*SL
0.051 + 0.018*SL
0.052 + 0.017*SL
0.093 + 0.010*SL
0.133 + 0.012*SL
Group2*
0.039 + 0.021*SL
0.053 + 0.016*SL
0.082 + 0.010*SL
0.135 + 0.010*SL
0.039 + 0.021*SL
0.054 + 0.016*SL
0.095 + 0.010*SL
0.141 + 0.010*SL
Group3*
0.033 + 0.021*SL
0.050 + 0.017*SL
0.082 + 0.010*SL
0.143 + 0.009*SL
0.035 + 0.021*SL
0.049 + 0.017*SL
0.096 + 0.010*SL
0.149 + 0.009*SL
A to Y
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
B to Y
*Group1 : SL < 4, *Group2 : =
Path
Parameter
Delay [ns]
SL = 2
0.057
0.063
0.095
0.141
0.060
0.064
0.107
0.146
<
Delay Equations [ns]
Group1*
0.037 + 0.010*SL
0.043 + 0.010*SL
0.083 + 0.006*SL
0.126 + 0.008*SL
0.040 + 0.010*SL
0.044 + 0.010*SL
0.096 + 0.006*SL
0.131 + 0.008*SL
Group2*
0.036 + 0.010*SL
0.049 + 0.009*SL
0.086 + 0.005*SL
0.133 + 0.006*SL
0.038 + 0.010*SL
0.050 + 0.009*SL
0.099 + 0.005*SL
0.138 + 0.006*SL
Group3*
0.028 + 0.011*SL
0.049 + 0.009*SL
0.088 + 0.005*SL
0.145 + 0.005*SL
0.031 + 0.011*SL
0.050 + 0.009*SL
0.101 + 0.005*SL
0.151 + 0.005*SL
A to Y
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
B to Y
*Group1 : SL < 4, *Group2 : =
Truth Table
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
1