
Samsung ASIC
5-27
STD130
SPSRAMBW_HD
High-Density Single-Port Synchronous Static RAM with Bit-Write
Application Notes
1.
Permitting Over-the-cell routing
In chip-level layout, over-the-cell routing in SPSRAMBW_HD is permitted for only Metal-5 and Metal-6
layers.
2.
Incoming power bus should be adjusted to guarantee NOT more than 10% voltage drop at typical-case
current levels.
3.
Power stripe should be tapped from both sides of SPSRAMBW_HD.
4.
A byte-write or word-write operation with SPSRAMBW_HD.
Refer to the function table. In byte-write operation, the number of BWEN[] signal bus should be divided
by a byte (8) and eight BWEN signals should be tied to a connection wire. In this case, DI[] bus is
controlled by a byte-wired BWEN signal instead of each BWEN bit. In word-write operation, the
functionality is exactly same as SPSRAM_HD. If all of BWEN[] signal is tied to low state, DI[] bus is only
controlled by WEN.
5.
Power reduction during standby mode.
The standby power is measured on the condition that only CSN is in disable mode and other signals are
in operation mode except that OEN is tied to low. If any of signals are activated while in standby mode,
the power will be consumed because the input switching activities are occurred by the signal transition.
Therefore, to reduce unnecessary power consumption, you should keep stable for all signals while in
standby mode.
<2-bank architecture >
RAM Core
W
D
X
W
D
RAM Core
Y-Dec &
Sense Amp.
Control Block
Y-Dec &
Sense Amp.
Y-Dec &
Sense Amp.
Control Block
Y-Dec &
Sense Amp.
RAM Core
W
D
X
W
D
RAM Core
I/O Driver
Address &
Clock Buffers
I/O Driver
VSS
VDD
VDD
VSS
VDD
VSS
VSS
VDD
VDD
VSS
VDD
VSS
D
D
A
W
O
C
C
D
D
B
B