
STD130
4-98
Samsung ASIC
PvSCKDCby
Input Clock Driver
Switching Characteristics
PSCKDC2
(Typical process, 25
°
C, 1.8V, t
R
/t
F
 = 1.50ns, SL: Standard Load)
PSCKDC4
PSCKDC6
PSCKDC8
Path
Parameter
Delay [ns]
 SL = 2
0.104
0.091
0.354
0.338
 < 
Delay Equations [ns]
Group1*
0.101 + 0.002*SL
0.088 + 0.002*SL
0.352 + 0.001*SL
0.336 + 0.001*SL
Group2*
0.081 + 0.002*SL
0.070 + 0.002*SL
0.353 + 0.001*SL
0.338 + 0.001*SL
Group3*
0.069 + 0.002*SL
0.057 + 0.002*SL
0.352 + 0.001*SL
0.337 + 0.001*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 275,   *Group2 : 275 < 
Path
Parameter
Delay [ns]
 SL = 2
0.139
0.120
0.473
0.455
 < 
Delay Equations [ns]
Group1*
0.138 + 0.001*SL
0.118 + 0.001*SL
0.472 + 0.000*SL
0.454 + 0.000*SL
Group2*
0.118 + 0.001*SL
0.099 + 0.001*SL
0.480 + 0.000*SL
0.459 + 0.000*SL
Group3*
0.100 + 0.001*SL
0.081 + 0.001*SL
0.480 + 0.000*SL
0.458 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 549,   *Group2 : 549 < 
Path
Parameter
Delay [ns]
 SL = 2
0.174
0.150
0.571
0.551
 < 
Delay Equations [ns]
Group1*
0.173 + 0.001*SL
0.149 + 0.001*SL
0.570 + 0.000*SL
0.550 + 0.000*SL
Group2*
0.153 + 0.001*SL
0.129 + 0.001*SL
0.586 + 0.000*SL
0.560 + 0.000*SL
Group3*
0.134 + 0.001*SL
0.109 + 0.001*SL
0.589 + 0.000*SL
0.561 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 823,   *Group2 : 823 < 
Path
Parameter
Delay [ns]
 SL = 2
0.203
0.180
0.658
0.635
 < 
Delay Equations [ns]
Group1*
0.203 + 0.000*SL
0.179 + 0.000*SL
0.657 + 0.000*SL
0.634 + 0.000*SL
Group2*
0.185 + 0.000*SL
0.157 + 0.000*SL
0.678 + 0.000*SL
0.649 + 0.000*SL
Group3*
0.166 + 0.000*SL
0.137 + 0.000*SL
0.686 + 0.000*SL
0.653 + 0.000*SL
PAD to Y
tR
tF
tPLH
tPHL
*Group1 : SL < 1096,   *Group2 : 1096 <