
Samsung ASIC
4-119
STD130
PHSOSCK1/K2/M1/M2/M3
3.3V InterfaceOscillator Cell with Enable
Switching Characteristics
PHSOSCK1
(Typical process, 25
°
C, 1.8V, 3.3V, t
R
/t
F
= 3.00ns, CL: Capacitive Load[pF])
(Typical process, 25
°
C, 1.8V, 3.3V, t
R
/t
F
= 3.00ns, SL: Standard Load)
Path
Parameter
Delay [ns]
CL = 50.0pF
1744.100
1367.900
842.620
686.330
1744.100
1367.900
842.390
685.650
<
Delay Equations [ns]
Group1*
36.850 + 34.145*CL
34.050 + 26.677*CL
25.820 + 16.336*CL
13.555 + 13.456*CL
36.850 + 34.145*CL
34.025 + 26.678*CL
25.590 + 16.336*CL
12.850 + 13.456*CL
Group2*
36.900 + 34.144*CL
33.900 + 26.680*CL
25.860 + 16.335*CL
13.590 + 13.455*CL
36.900 + 34.144*CL
33.900 + 26.680*CL
25.570 + 16.336*CL
12.950 + 13.454*CL
Group3*
36.900 + 34.144*CL
33.900 + 26.680*CL
25.800 + 16.336*CL
13.500 + 13.456*CL
36.900 + 34.144*CL
33.900 + 26.680*CL
25.600 + 16.336*CL
12.800 + 13.456*CL
PADA to
PADY
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
E to PADY
*Group1 : CL < 50, *Group2 : 50 =
Path
Parameter
Delay [ns]
SL = 2
0.065
0.059
33.265
31.307
0.065
0.059
32.613
29.892
<
Delay Equations [ns]
Group1*
0.060 + 0.002*SL
0.053 + 0.003*SL
33.262 + 0.001*SL
31.303 + 0.002*SL
0.060 + 0.002*SL
0.053 + 0.003*SL
32.610 + 0.001*SL
29.888 + 0.002*SL
Group2*
0.061 + 0.002*SL
0.055 + 0.002*SL
33.262 + 0.001*SL
31.303 + 0.002*SL
0.060 + 0.002*SL
0.055 + 0.002*SL
32.610 + 0.001*SL
29.888 + 0.002*SL
Group3*
0.059 + 0.002*SL
0.053 + 0.003*SL
33.266 + 0.001*SL
31.307 + 0.002*SL
0.061 + 0.002*SL
0.053 + 0.003*SL
32.614 + 0.001*SL
29.892 + 0.002*SL
PADA to
YN
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
E to YN
*Group1 : SL < 4, *Group2 : =