
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
517
Figure 41 RDCC Port Functional Timing
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
D6
D5
D4
D3
D2
D1
D12
D11
D10
D9
D8
D7
D6
D5
D4
RSLDSEL = 0
RSLDSEL = 1
ROHFP
RLDCLK
RLD
RSLDCLK
RSLD
RSLDCLK
RSLD
18.8 Transmit DCC Port Timing (TDCC)
The function of the transmit section and line TDCC block is to serially input from the TLD and
the TSLD ports the DCC bytes to be inserted in the next transmit frame. The line DCC bytes
(D4-D12) are input from TLD. TSLD is selectable to input either the section DCC bytes (D4-
D12) or the line DCC bytes (D1-D3). The TRMP TSLDSEL register bit selects which of the
two inputs is multiplexed onto TSLD.
Figure 29 shows the TDCC functional timings. TLDCLK is the generated output clock used to
provide timing for the TLD input. TLDCLK is a nominal 576 KHz clock. TSLDCLK is the
generated output clock used to provide timing for the TSLD input. If TSLD carries the line
DCC, TSLDCLK is a nominal 576 KHz clock or if TSLD carries the section DCC, TSLDCLK
is a nominal 192 KHz clock. Sampling TOHFP high identifies the MSB of the first DCC byte
on TLD (D4) and TSLD (D1 or D4). TLD and TSLD data should be externally aligned with the
falling edge of TLDCLK and TSLDCLK. When STS-192/STM-64 mode active, TDCC ports 2-
4 are ignored.