
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
225
Indirect Address
IADDR[7:0]
1011 1111
Indirect Data
1100 0000
First byte of the 16/64 byte expected trace
1100 0001
to
1111 1111
Other bytes of the 16/64 byte expected trace
RWB
The active high read and active low write (RWB) bit selects if the current access to the
internal RAM is an indirect read or an indirect write. Writing to the Indirect Address
Register initiates an access to the internal RAM. When RWB is set to logic 1, an indirect
read access to the RAM is initiated. The data from the addressed location in the internal
RAM will be transferred to the Indirect Data Register. When RWB is set to logic 0, an
indirect write access to the RAM is initiated. The data from the Indirect Data Register will
be transferred to the addressed location in the internal RAM.
BUSY
The active high RAM busy (BUSY) bit reports if a previously initiated indirect access to the
internal RAM has been completed. BUSY is set to logic 1 upon writing to the Indirect
Address Register. BUSY is set to logic 0, upon completion of the RAM access. This
register should be polled to determine when new data is available in the Indirect Data
Register.