
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
45
Pin Name
Type
Pin
No.
Function
PHASE_ERR4
PHASE_ERR3
PHASE_ERR2
PHASE_ERR1
Input
D1
E2
L8
G4
The
phase error
(PHASE_ERR) inputs indicates when the
TXCLK[N]_p/n output is not aligned with the corresponding
TXDATA[N]_p/n bus. When asserted, the receiving device
cannot use the source synchronous TXCLK[N]_p/n to
sample the corresponding TXDATA[N]_p/n bus.
PHASE_ERR[N] are treated as asynchronous signals and
are used to trigger maskable interrupts. In addition, the
associated PHASE_INIT[N] output should be asserted to
reinitiate alignment under user control.
For quad STS-48/STM-16 mode, PHASE_ERR[N] indicates
a phase alignment error for the corresponding transmit
TXCLK[N]_p/n clock and TXDATA[N]_p/n data bus.
For STS-192/STM-64 mode, PHASE_ERR1 indicates a
phase alignment error for the TXCLK2 clock (the OC-192
mode clock) and the TXDATA[4:1]_p/n[3:0] bus.
PHASE_ERR2, PHASE_ERR3 and PHASE_ERR4 are
ignored.
PHASE_ERR[4:1] is a low speed asynchronous input.
PHASE_INIT4
PHASE_INIT3
PHASE_INIT2
PHASE_INIT1
Output
H5
J6
K7
F3
The
phase initiatilization
(PHASE_INIT) outputs indicates
to the receiving device that the device should start the
TXCLK[N]_p/n and TXDATA[N]_p/n alignment process. The
PHASE_INIT[N] outputs are directly sourced from the
SPECTRA-9953 STLI-192 Phase Alignment register.
PHASE_INIT[4:1] is a low speed asynchronous output.