
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
136
Register 0002H: SP9953 Receive Configuration 2
Bit
Type
Function
Default
Bit 15
R/W
RSTS12C[16]
0
Bit 14
R/W
RSTS12C[15]
0
Bit 13
R/W
RSTS12C[14
0
Bit 12
R/W
RSTS12C[13]
0
Bit 11
R/W
RSTS12C[12]
0
Bit 10
R/W
RSTS12C[11]
0
Bit 9
R/W
RSTS12C[10]
0
Bit 8
R/W
RSTS12C[9]
0
Bit 7
R/W
RSTS12C[8]
0
Bit 6
R/W
RSTS12C[7]
0
Bit 5
R/W
RSTS12C[6]
0
Bit 4
R/W
RSTS12C[5]
0
Bit 3
R/W
RSTS12C[4]
0
Bit 2
R/W
RSTS12C[3]
0
Bit 1
R/W
RSTS12C[2]
0
Bit 0
R/W
RSTS12C[1]
0
The Receive Configuration 2 Register is provided at SP9953 Read/Write Address 02H.
RSTS12C[1:16]
The receive STS-12 concatenation mode (RSTS12C[1:16 bits enable the processing of an
STS-12c (VC-4-4c) payload for the corresponding STS-12/STM-4 slice. When a logic 1 is
written to RSTS12CSL[X] and a logic 1 is written to RSTS12C[X], the receive STS-
12/STM-4 slice processes a slave STS-12c (VC-4-4c) payload. When a logic 0 is written to
RSTS12CSL[X] and a logic 1 is written to RSTS12C[X], the receive STS-12/STM-4 slice
process a master STS-12c (VC-4-4c) payload. When a logic 0 is written to RSTS12CSL[X]
and a logic 0 is written to RSTS12C[X], the receive STS-12/STM-4 slice is not processing a
STS-12c (VC-4-4c) payload.
Note: there is a possibility that SVCA indirect registers can be corrupted upon path
reconfiguration. Refer to section 14.13 for more explanation and how to avoid the problem.