
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
164
Register 001FH: Clocks Activity Monitors
Bit
Type
Function
Default
Bit 15
R
RCLKACT_155_4
0
Bit 14
R
RCLKACT_155_3
0
Bit 13
R
RCLKACT_155_2
0
Bit 12
R
RCLKACT_155_1
0
Bit 11
R
RCLKACT_77_4
0
Bit 10
R
RCLKACT_77_3
0
Bit 9
R
RCLKACT_77_2
0
Bit 8
R
RCLKACT_77_1
0
Bit 7
R
TCLKACT_155_4
0
Bit 6
R
TCLKACT_155_3
0
Bit 5
R
TCLKACT_155_2
0
Bit 4
R
TCLKACT_155_1
0
Bit 3
R
TCLKACT_77_4
0
Bit 2
R
TCLKACT_77_3
0
Bit 1
R
TCLKACT_77_2
0
Bit 0
R
TCLKACT_77_1
0
This register provides line clocks activity monitors. These bits do not necessarily detect
clocking problems such as floating clocks
RCLKACT_155_[1:4]
The receive line activity monitor (RCLKACT_155_[1:4]) signals are event detectors.
RCLKACT_155_[X] is asserted when a low to high transition occurs on the internal 155
MHz receive clock of slice X. RCLKACT_155 [X] is cleared when the line activity
monitor register is read.
RCLKACT_77_[1:4]
The receive line activity monitor (RCLKACT_77_[1:4]) signals are event detectors.
RCLKACT_77_[X] is asserted when a low to high transition occurs on the internal 77 MHz
receive clock of slice X. RCLKACT_77 [X] is cleared when the line activity monitor
register is read..
TCLKACT_155_[1:4]
The receive line activity monitor (TCLKACT_155_[1:4]) signals are event detectors.
TCLKACT_155_[X] is asserted when a low to high transition occurs on the internal 155
MHz receive clock of slice X. TCLKACT_155 [X] is cleared when the line activity
monitor register is read.