
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
169
Register 0030H-003F: SP9953 Interrupt Status #1 to #16
Bit
Type
Function
Default
Bit 15
R/W
INTE[N]
0
Bit 14
R
R8TDI[N]
X
Bit 13
R
SHPII[N]
X
Bit 12
R
TSVCAI[N]
X
Bit 11
R
DLLI
X
Bit 10
R
CSTRI
X
Bit 9
R
STLII
X
Bit 8
R
SRLII
X
Bit 7
R
T8TEI[N]
X
Bit 6
R
SARCI[N]
X
Bit 5
R
RSVCAI[N]
X
Bit 4
R
PATHRTTPI[N]
X
Bit 3
R
RHPPI[N]
X
Bit 2
R
SBERI[N]
X
Bit 1
R
RTTPI[N]
X
Bit 0
R
RRMPI[N]
X
The Interrupt Status Registers are provided at SP9953 Read/Write Address 30H to 3FH.
RRMPI[N]…R8TDI[N]
The RRMPI[N] to R8TDI[N] are interrupt status indicators for the corresponding block
within the STS-12/STM-4 Nth slice. The interrupt status is set to logic 1 to indicate a
pending interrupt from the corresponding block. The interrupt status bits are independent of
the interrupt enable bit.
Note that CSTRI, STLII, SRLII and DLLI are defined only for N=1. All others are kept at
zero.
Note that SARCI, SBERI, RTTPI are defined only for N=1,5,9,13. All others are kept at
zero.
INTE[N]
The interrupt enable (INTE[N]) bit controls the activation of the interrupt (INTB) output.
When a logic 1 is written to INTE[N], the RRMP[N]…R8TD[N] pending interrupt will
assert the interrupt (INTB) output. When a logic 0 is written to INTE[N], the
RRMP[N]…R8TD[N] pending interrupt will not assert the interrupt (INTB) output.