
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
505
Figure 32 Boundary Scan Architecture
Boundary Scan
Register
Control
TDI
TDO
Device Identification
Register
Bypass
Register
Instruction
Register
and
Decode
TRSTB
TMS
TCK
Test
Access
Port
Controller
Mux
DFF
Select
Tri-state Enable
The boundary scan architecture consists of a TAP controller, an instruction register with
instruction decode, a bypass register, a device identification register, and a boundary scan
register. The TAP controller interprets the TMS input and generates control signals to load the
instruction and data registers. The instruction register with instruction decode block is used to
select the test to be executed and/or the register to be accessed. The bypass register offers a
single-bit delay from primary input, TDI to primary output, TDO. The device identification
register contains the device identification code.
The boundary scan register allows testing of board inter-connectivity. The boundary scan
register consists of a shift register place in series with device inputs and outputs. Using the
boundary scan register, all digital inputs can be sampled and shifted out on primary output,
TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital
outputs.