
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
172
Register 004FH: DLL Control Status
Bit
Type
Function
Default
Bit 15-8
R
RESERVED
X
Bit 7
R
SYSCLKI
X
Bit 6
R
REFCLKI
X
Bit 5
R
ERRORI
X
Bit 4
R
CHANGEI
X
Bit 3
Unused
X
Bit 2
R
ERROR
X
Bit 1
R
CHANGE
0
Bit 0
R
RUN
0
The DLL Control Status Register provides information of the DLL operation.
RUN
The DLL lock status register bit (RUN) indicates the DLL found a delay line tap in which
the phase difference between the rising edge of REFCLK and the rising edge of SYSLCK is
zero. After system reset, RUN is logic zero until the phase detector indicates an initial lock
condition. When the phase detector indicates lock, RUN is set to logic 1.
The RUN register bit is cleared only by a system reset
or a software reset (writing to
register 4EH).
CHANGE
The delay line tap change register bit (CHANGE) indicates the DLL has moved to a new
delay line tap. CHANGE is set high for eight SYSCLK cycles when the DLL moves to a
new delay line tap.
ERROR
The delay line error register bit (ERROR) indicates the DLL has run out of dynamic range.
When the DLL attempts to move beyond the end of the delay line, ERROR is set high.
When ERROR is high, the DLL cannot generate a DLLCLK phase which causes the rising
edge of REFCLK to be aligned to the rising edge of SYSCLK. ERROR is set low, when
the DLL captures lock again.
CHANGEI
The delay line tap change event register bit (CHANGEI) indicates the CHANGE register bit
has changed value. When the CHANGE register changes from a logic zero to a logic one,
the CHANGEI register bit is set to logic one.