
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
512
Figure 36 TXFPI/TXFPO Functional Timing
txdata[1]
txdata[2]
txdata[3]
txdata[4]
txfpi
6
F
6
F
8
2
8
2
A1
A2
J0
1st A1 bit to TXFPI = [9.56 ns ; 112 ns]
txfpo
TXFPO to 1st A1 bit = 44 ns
TXFPO pulse width is 12.86ns
S
note : txfpi is asynchronously edge detected.
18.2 System Add Interface
Figure 30 shows the relative timing of the add system interface. The LVDS links carry
SONET/SDH frame octets that are encoded in 8B/10B characters. Frame boundaries,
justification events, and alarm conditions are encoded in special control characters. The
upstream devices sourcing the links share a common clock and have a common transport frame
alignment that is synchronized by the Add Serial Interface Frame Pulse signal (AFP). Due to
phase noise from clock multiplication circuits and backplane routing discrepancies, the links
will not phase aligned to each other will be frequency locked The delay from AFP being
sampled high to the first and last J0 character is shown in Figure 37. In this example, the first
J0 is delivered on link ADX[N]. The delay to the last J0 represents the time when the all the
links have delivered their J0 character. In the example below, link ADY[M] is shown to be the
slowest. The minimum value for the internal programmable delay (AFPDLY[13:0]) is the delay
to the last J0 character plus 20. The maximum value is the delay to the first J0 character plus
36. Consequently, the external system must ensure that the relative delays between all the add
LVDS links be less than 16 bytes. The relative phases of the links in Figure 37 are shown for
illustrative purposes only. Links may have different delays relative to other links than what is
shown.
Also note that changes to AFPDLY[13:0] will only take effect after an AFP pulse has been
received, (and while AFP_DISABLE is not set to 1).