
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
374
Register 2060H: STLI Configuration
Bit
Type
Function
Default
Bit 15
Unused
Bit 14
Unused
Bit 13
Unused
Bit 12
Unused
Bit 11
R/W
Reserved
1
Bit 10
R/W
Reserved
1
Bit 9
R/W
Reserved
1
Bit 8
R/W
Reserved
1
Bit 7
R/W
PHASE_INIT[4]
0
Bit 6
R/W
PHASE_INIT[3]
0
Bit 5
R/W
PHASE_INIT[2]
0
Bit 4
R/W
PHASE_INIT[1]
0
Bit 3
R/W
INTERLEAVEEN4
1
Bit 2
R/W
INTERLEAVEEN3
1
Bit 1
R/W
INTERLEAVEEN2
1
Bit 0
R/W
INTERLEAVEEN1
1
INTERLEAVEEN[4:1]
The 4 byte interleave enable one (INTERLEAVEEN1) bit controls the 4 byte interleave
rotation matrix in both STS-192/STM-64 and in quad STS-48/STM-16 modes. In STS-
192/STM-64 mode, only INTERLEAVEEN1 is active and INTERLEAVEEN[4:3] has no
effect. In quad STS-48/STM-16 mode, INTERLEAVEEN[n] bit controls the 4 byte
interleave rotation matrix in the corresponding STS-48c (STM-16c) #n data stream. These
bits should be set to there default values for normal operation.
PHASE_INIT[4:1]
The Phase Initialization register bits control the logic levels of the PHASE_INIT[N]
outputs. If set to logic 0, the corresponding PHASE_INIT[N] output will be set low. If set
to logic 1, the corresponding PHASE_INIT[N] output will be set high.
Reserved
The Reserved bits should be set to their default values for proper operation of the
SPECTRA-9953.