
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
121
Code
Group
Name
Curr. RD-
abcdei fghj
Curr. RD+
abcdei fghj
Decoded Signals
Description
OD[7:0] = ‘h00
K28.6
001111 0110
110000 1001
OJ1=’b1’
High-order path frame alignment
OD[7:0] = ‘h00
14.20 Add/Drop Clock Synthesis Unit
The CSU is a fully integrated clock synthesis unit. It generates low jitter multi-phase
differential clocks at 777.6 MHz for use by the Add bus DRU and the Drop bus PISO.
14.21 Drop bus Transmit Serializer
The Drop bus PISO is a parallel-to-serial converter designed for high-speed transmit operation,
supporting up to 777.6 Mbit/s. It converts 8B/10B characters to bit-serial format.
There are 16 instances of the PISO on the SPECTRA-9953 device.
14.22 Drop bus LVDS Transmitter
The TXLV block is a 777.6 Mbit/s Low Voltage Differential Signaling (LVDS) Transmitter
according to the IEEE 1596.3-1996 LVDS specification.
The TXLV accepts 777.6 Mbit/s differential data from a “parallel-in, serial-out” (PISO) circuit
and then transmits the data off-chip as a low voltage differential signal on TP[X]/TN[X] pins.
The TXLV uses a reference current and voltage from the TXLVREF block to control the output
differential voltage amplitude and the output common-mode voltage.
14.23 Transmit Reference Generator
The TXLVREF provides an on-chip bandgap voltage reference (1.20V ±5%) and a precision
current to the TXLV (777.6 Mbit/s LVDS Transmitter) block’s. The reference voltage is used to
control the common-mode level of the TXLV output, while the reference current is used to
control the output amplitude.
The precision currents are generated by forcing the reference voltage across an external, off-
chip 3.16 k (±1%) resistor. The resulting current is then mirrored through several individual
reference current outputs, so each TXLV receives its own reference current.
There is one instance of the TXREF for the SPECTRA-9953 device.