
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
132
Register 0000H: SP9953 Master Configuration
Bit
Type
Function
Default
Bit 15
R
TIP
X
Bit 14
R
QUAD2488
X
Bit 13
R/W
Unused
0
Bit 12
R/W
Unused
0
Bit 11
R/W
Unused
0
Bit 10
R/W
Unused
0
Bit 9
R/W
Unused
0
Bit 8
R/W
Unused
0
Bit 7
R/W
Reserved
0
Bit 6
R/W
WCIMODE
0
Bit 5
R/W
RESET_CORE
0
Bit 4
R/W
RESETSL[4]
0
Bit 3
R/W
RESETSL[3]
0
Bit 2
R/W
RESETSL[2]
0
Bit 1
R/W
RESETSL[1]
0
Bit 0
R/W
RESET
0
The Master Configuration Register is provided at SP9953 Read/Write Address 00H.
RESET
The software reset (RESET) bit resets the whole device. When a logic 1 is written to
RESET, the SP9953 is held in reset. When a logic 0 is written to RESET, the SP9953
operates normally.
RESETSL[1:4]
The slice software reset (RESETSL[1:4]) bits reset the corresponding STS-48/STM-16
slice. When a logic 1 is written to RESETSL[X], the STS-48/STM-16 slice is held in reset.
When a logic 0 is written to RESETSL[X], the STS-48/STM-16 slice operates normally.
Note that top-level registers with slice configuration are not reset with these bits.
RESET_CORE
The digital core software reset (CORE_RESET) bit along with the RESETSL[1:4] can be used
to reset the whole digital core (The analog interfaces are not reset). When a logic 1 is written to
CORE_RESET and RESETSL[1:4], the digital core is kept into a reset state. When a logic 0 is
written to RESET_CORE and RESETSL[1:4], the digital core operates normally.
Notes:
(1) No top-level registers are reset with this bit.