
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
267
Register 00E1H: SARC Indirect Read/Write Data
Bit
Type
Function
Default
Bit 15
R/W
DATA[15]
0
Bit 14
R/W
DATA[14]
0
Bit 13
R/W
DATA[13]
0
Bit 12
R/W
DATA[12]
0
Bit 11
R/W
DATA[11]
0
Bit 10
R/W
DATA[10]
0
Bit 9
R/W
DATA[9]
0
Bit 8
R/W
DATA[8]
0
Bit 7
R/W
DATA[7]
0
Bit 6
R/W
DATA[6]
0
Bit 5
R/W
DATA[5]
0
Bit 4
R/W
DATA[4]
0
Bit 3
R/W
DATA[3]
0
Bit 2
R/W
DATA[2]
0
Bit 1
R/W
DATA[1]
0
Bit 0
R/W
DATA[0]
0
DATA[15:0]
The indirect access data (DATA[15:0]) bits hold the data transfer to or from the internal
Indirect Registers during indirect access. When RWB is set to logic 1 (indirect read), the
data from the addressed location in the internal Indirect Registers will be transferred to
DATA[15:0]. BUSY should be polled to determine when the new data is available in
DATA[15:0]. When RWB is set to logic 0 (indirect write), the data from DATA[15:0] will
be transferred to the addressed location in the internal Indirect Registers. The indirect
(Write) Data register must contain valid data before the indirect write is initiated by writing
to the Indirect Address Register. DATA[15:0] has a different meaning depending on which
address of the internal Indirect Registers is being accessed.