
PM5317 SPECTRA-9953 Telecom Standard Product Data Sheet
Release
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000741, Issue 5
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Features
2.1 General
The PM5317 SPECTRA-9953 is a single channel STS-192/STM-64 or four channels STS-
48/STM-16 monolithic SONET/SDH Payload Extractor and Aligner for use with single STS-
192c (STM-64/AU4-64c), single STS-192 (STM-64/AU4-16c/AU4-4c/AU4/AU3), quad STS-
48c (STM-16/AU4-16c), or quad STS-48 (STM-16/AU4-4c/AU4/AU3) interface applications
operating at serial interface speeds of up to 9953 Mbit/s.
In single STS-192/STM-64 mode, supports a duplex 16-bit 622 MHz LVDS line side
interface for direct connection to external clock recovery, clock synthesis, and serializer-
deserializer (SERDES) components. The interface is compatible with OIF-99 SFI-4
specifications.
In quad STS-48/STM-16 mode, supports four duplex 4-bit 622 MHz LVDS line side
interfaces to directly connect to external clock recovery, clock synthesis, and SERDES
components. Supports direct interface to the PM5395 CRSU-4x2488 4xOC48 serializer
Provides termination for SONET Section, Line and Path overhead or SDH Regenerator
Section, Multiplexer Section, and High Order Path overhead.
In single STS-192/STM-64 mode, provides a 16-bit 777.7 MHz LVDS Add and Drop Serial
TelecomBus with extended 8B/10B-based encoding.
In quad STS-48/STM-16 mode, provides four 4-bit 777.7 MHz LVDS Add and Drop Serial
TelecomBus interfaces with extended 8B/10B-based encoding.
Maps SONET/SDH payloads to system timing, accommodating plesiochronous timing
offsets between the line and system timing references, through pointer processing.
Supports Space Slot Interchange (SSI) functions at the Drop and Add TelecomBuses for
switching any legal mix of STS-12/STM-4 SONET/SDH streams.
Supports line loopback from the line side receive stream to the transmit stream and
diagnostic loopback from an Add TelecomBus interface to a Drop TelecomBus interface.
Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test
purposes.
Provides a generic 16-bit microprocessor bus interface for configuration, control, and status
monitoring.
Low power 1.8 V CMOS core logic with 3.3 V CMOS/TTL compatible digital inputs and
digital outputs.
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Wide temperature range (-40 C to +105 C).
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1152 pin Flip-Chip BGA (FCBGA) package.